DSM2180F3-15T6(2001) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
DSM2180F3-15T6
(Rev.:2001)
(Rev.:2001)
STMicroelectronics
DSM2180F3-15T6 Datasheet PDF : 63 Pages
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DSM2180F3
SUMMARY DESCRIPTION
These are system memory devices for use with
Digital Signal Processors from the popular Analog
Devices ADSP-218X family. DSM means Digital
signal processor System Memory. A DSM device
brings in-system programmable Flash memory,
programmable logic, and additional I/O to DSP
systems. The result is a simple and flexible two-
chip solution for DSP designs. DSM devices pro-
vide the flexibility of Flash memory and smart
JTAG programming techniques for both manufac-
turing and the field. On-chip integrated memory
decode logic and memory paging logic make it
easy to add large amounts of external Flash mem-
ory to the ADSP-218X family for bootloading upon
power-up and/or overlay memory. The DSP ac-
cesses this Flash memory using either its Byte
DMA (BDMA) interface or as external data overlay
memory (no DMA setup overhead).
Figure 2. PLCC Connections
PD2
8
PD1
9
PD0
10
PC7
11
PC6
12
PC5
13
PC4
14
VCC
15
GND
16
PC3
17
PC2
18
PC1
19
PC0
20
46
AD15
45
AD14
44
AD13
43
AD12
42
AD11
41
AD10
40
AD9
39
AD8
38
VCC
37
AD7
36
AD6
35
AD5
34
AD4
AI02857
JTAG In-System Programming (ISP) reduces de-
velopment time, simplifies manufacturing flow,
and lowers the cost of field upgrades. The JTAG
ISP interface eliminates the need for sockets and
pre-programmed memory and logic devices. For
manufacturing, end products may be assembled
with a blank DSM device soldered to the circuit
board and programmed at the end of the manufac-
turing line in 10 to 20 seconds with no involvement
of the DSP. This allows efficient means to test
product and manage inventory by rapidly pro-
gramming test code, then application code as de-
termined by inventory requirements (Just-In Time
inventory). Additionally, JTAG ISP reduces devel-
opment time by turning fast iterations of DSP code
in the lab. Code updates in the field require no dis-
assembly of product. The FlashLINKTM JTAG pro-
gramming cable costs $59 USD and plugs into any
PC or note-book parallel port.
Figure 3. PQFP Connections
PD2 1
PD1 2
PD0 3
PC7 4
PC6 5
PC5 6
PC4 7
VCC 8
GND 9
PC3 10
PC2 11
PC1 12
PC0 13
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
31 VCC
30 AD7
29 AD6
28 AD5
27 AD4
AI02858
In addition to ISP Flash memory, DSM devices
add programmable logic (PLD) and up to 16 con-
figurable I/O pins to the DSP system. The state of
each I/O pin can be driven by DSP software or
PLD logic. PLD and I/O configuration are program-
mable by JTAG ISP, just like the Flash memory.
The PLD consists of more than 3000 gates and
has 16 macro cell registers. Common uses for the
PLD include chip selects for external devices (i.e.
UART), state-machines, simple shifters and
counters, keypad and control panel interfaces,
clock dividers, handshake delay, muxes, etc. This
eliminates the need for small external PLDs and
logic devices. Configuration of PLD, I/O, and Flash
memory mapping are easily entered in a point-
and-click environment using the software develop-
ment tool, PSDsoft ExpressTM. This software is
available at no charge from www.psdst.com.
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