RT9032CGQW View Datasheet(PDF) - Richtek Technology
Part Name
Description
Manufacturer
RT9032CGQW Datasheet PDF : 13 Pages
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RT9032
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
PD(MAX) = (TJ(MAX) − TA) /θJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance (θJA is layout dependent) for
WDFN-8L 2x2 is 165°C/W and WQFN-8L 1.6x1.6 (COL)
is 175°C/W on the standard JEDEC 51-3 single-layer
thermal test board. The maximum power dissipation at TA
= 25°C can be calculated by following formula :
PD(MAX) = (125°C − 25°C) / (165°C/W) = 0.606W for
WDFN-8L 2x2 packages
PD(MAX) = (125°C − 25°C) / (175°C/W) = 0.571W for
WQFN-8L 1.6x1.6 (COL) packages
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA. The Figure 2 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power allowed.
0.7
WDFN-8L 2x2
0.6
Single Layer PCB
0.5
0.4 WQFN-8L 1.6x1.6
0.3
0.2
0.1
0
0 15 30 45 60 75 90 105 120 135
Ambient Temperature (°C)
Figure 2. Derating Curve of Maximum Power Dissipation
Layout Considerations
Careful PCB Layout is necessary for better performance.
The following guidelines should be followed for good PCB
layout.
` Place the input and output capacitors as close as possible
to the IC.
` Keep VIN, VOUT1 and VOUT2 traces as possible as
short and wide.
` Connect GND pin and Exposed Pad to a large PCB
ground plane for maximum thermal dissipation.
CIN should be placed as
close as possible to VIN
pin for good filtering.
COUT1 & COUT2 should
be placed as close as
possible to VOUT pin for
good filtering.
CIN
VIN 1
EN1 2
P2 3
P1 4
8 VOUT1
7 VOUT2
6 GND
9 5 EN2
COUT1
COUT2
The exposed pad should be
connected to a strong ground
plane for heat sinking and
noise reduction.
Figure 3. Layout Considerations for WDFN-8L 2x2
Packages
CIN should be placed as
close as possible to VIN
pin for good filtering.
COUT1
COUT1 & COUT2 should
be placed as close as
possible to output pin for
good filtering.
CIN
VOUT1
8
VIN 1
7 VOUT2
EN1 2
6 P2
EN2 3
5 GND
4
COUT2
P1
GND
Figure 4. Layout Considerations for WQFN-8L 1.6x1.6
(COL) Packages
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
DS9032-03 August 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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