24LCS21SN View Datasheet(PDF) - Microchip Technology
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24LCS21SN Datasheet PDF : 24 Pages
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24LCS21
2.0 FUNCTIONAL DESCRIPTION
The 24LCS21 operates in two modes, the Transmit-
Only mode and the Bidirectional mode. There is a
separate two-wire protocol to support each mode, each
having a separate clock input but sharing a common
data line (SDA). The device enters the Transmit-Only
mode upon power-up. In this mode, the device
transmits data bits on the SDA pin in response to a
clock signal on the VCLK pin. The device will remain in
this mode until a valid high-to-low transition is placed
on the SCL input. When a valid transition on SCL is
recognized, the device will switch into the Bidirectional
mode. The only way to switch the device back to the
Transmit-Only mode is to remove power from the
device.
2.1 Transmit-Only Mode
The device will power-up in the Transmit-Only mode at
address 00h. This mode supports a unidirectional two-
wire protocol for continuous transmission of the
contents of the memory array. This device requires that
it be initialized prior to valid data being sent in the
FIGURE 2-1:
TRANSMIT-ONLY MODE
SCL
TVAA
TVAA
Transmit-Only mode (see Initialization Procedure,
below). In this mode, data is transmitted on the SDA pin
in 8-bit bytes, with each byte followed by a ninth, null bit
(Figure 2-1). The clock source for the Transmit-Only
mode is provided on the VCLK pin, and a data bit is out-
put on the rising edge on this pin. The eight bits in each
byte are transmitted Most Significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the internal Address Pointers will wrap around to the
first memory location (00h) and continue. The
Bidirectional mode clock (SCL) pin must be held high
for the device to remain in the Transmit-Only mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the Trans-
mit-Only mode. Nine clock cycles on the VCLK pin must
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit in address 00h.
(Figure 2-2).
SDA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB)
Bit 7
VCLK
FIGURE 2-2:
VCC
SCL
TVHIGH
TVLOW
DEVICE INITIALIZATION
SDA
VCLK
High-impedance for 9 clock cycles
TVPU
1
2
8
TVAA
TVAA
Bit 8
Bit 7
9
10
11
DS21127F-page 4
© 2005 Microchip Technology Inc.
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