24LC41-IP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
24LC41-IP Datasheet PDF : 18 Pages
| |||
24LC41
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read. These operations are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port and are completely
independent of one another.
7.1 Current Address Read
The port contains an address counter that maintains
the address of the last word accessed, internally incre-
mented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to one, the port issues an acknowledge
and transmits the 8-bit data word. The master will not
acknowledge the transfer but does generate a Stop
condition and the port discontinues transmission
(Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
port as part of a write operation. After the word address
is sent, the master generates a Start condition following
the acknowledge. This terminates the write operation,
but not before the internal address pointer is set. The
master then issues the control byte again, but with
the R/W bit set to a one. The port then issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer but does
generate a Stop condition and the port discontinues
transmission (Figure 7-2).
FIGURE 7-1:
CURRENT ADDRESS READ
S
Bus Activity
T
Master
A
R
T
Control
Byte
DSDA or
MSDA Line
S
BUS Activity
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the port transmits the
first data byte, and the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the port to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads, the port contains an
internal address pointer, which is incremented by one
at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
7.4 Noise Protection
Both the DDC Monitor Port and Microcontroller Access
Port employ a VCC threshold detector circuit which
disables the internal erase/write logic, if the VCC is
below 1.5 volts at nominal conditions.
The DSCL, MSCL, DSDA and MSDA inputs have
Schmitt Trigger and filter circuits which suppress noise
spikes to assure proper device operation even on a
noisy bus.
Data n
A
C
K
S
T
O
P
P
N
O
A
C
K
2004 Microchip Technology Inc.
DS21140F-page 11
Share Link: 