MAX5804AUB(2013) View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX5804AUB
(Rev.:2013)

Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output Voltage DACs with Internal Reference and I2C Interface

Maxim Integrated 

MAX5803/MAX5804/MAX5805

Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output

Voltage DACs with Internal Reference and I2C Interface

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)

(Note 2)

Note 2: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range

are guaranteed by design and characterization. Typical specifications are at TA = +25°C.

Note 3: DC Performance is tested without load.

Note 4: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.

Note 5: Gain and offset calculated from measurements made with VREF = VDD at code 30 and 4065 for MAX5805, code 8 and

1016 for MAX5804, and code 2 and 254 for MAX5803.

Note 6: Subject to zero and full-scale error limits and VREF settings.

Note 7: On power-up, the device initiates an internal 200Fs (typ) calibration sequence. All commands issued during this time will

be ignored.

Note 8: Specification is guaranteed by design and characterization.

Note 9: Static logic inputs with VIL = VGND and VIH = VDDIO.

Note 10: An unconnected condition on ADDR is sensed via a resistive pullup and pulldown operation; for proper operation, ADDR

should be tied to VDDIO, GND, or left unconnected with minimal capacitance.

SDA

tf

SCL

tCLPW

S

tLOW

tSU;DAT

tr

tf

tHD;STA

tHD;DAT

tHIGH

tSU;STA

Sr

CLR

LDAC

tCLRSTA

tHD;STA

tSP

tr

tBUF

t SU ;STO

P

S

tLDH

tLDPW

Figure 1. I2C Serial Interface Timing Diagram

Maxim Integrated

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