27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
RGB_IN
1
CNTL_IN
0
DE_IN
OUT
CMF
PCLK_IN
RNG0
RNG1
PWRDWN
PLL
TIMING AND
CONTROL
MAX9217
VCC
130Ω
130Ω
*
1
*
IN
0
82Ω
82Ω
RNG0
RNG1
PLL
TIMING AND
CONTROL
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
*CAPS CAN BE AT EITHER END.
Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link
R/F
OUTEN
RGB_OUT
CNTL_OUT
DE_OUT
PCLK_OUT
REFCLK
PWRDWN
LOCK
RGB_IN
1
CNTL_IN
0
DE_IN
OUT
CMF
PCLK_IN
RNG0
RNG1
PWRDWN
PLL
TIMING AND
CONTROL
MAX9217
VCC
130Ω
130Ω
1
IN
0
82Ω
82Ω
RNG0
RNG1
PLL
TIMING AND
CONTROL
MAX9218
R/F
OUTEN
RGB_OUT
CNTL_OUT
DE_OUT
PCLK_OUT
REFCLK
PWRDWN
LOCK
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link
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