DS1859B-020 View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
DS1859B-020
Maxim Integrated
DS1859B-020 Datasheet PDF : 28 Pages
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Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
Table 4. ADEN Address Configuration
ADEN
(ADDRESS
ENABLE)
NO. OF SEPARATE
DEVICE
ADDRESSES
ADDITIONAL
INFORMATION
0
2
See Figure 2
1
1 (Main Device only) See Figure 3
Table 5. ADEN and ADFIX Bits
ADEN
0
0
1
1
ADFIX
0
1
0
1
AUXILIARY
ADDRESS
A0h
A0h
N/A
N/A
MAIN ADDRESS
A2h
EEPROM
(Table 01, 8Ch)
A2h
EEPROM
(Table 01, 8Ch)
MAIN DEVICE ENABLE
AUXILIARY DEVICE ENABLE
DEC
0
95
96
127
128
143
0
0
AUXILIARY
DEVICE
EN
EN
MAIN
DEVICE
5Fh
60h
EN
7Fh
7Fh
TABLE SELECT
DECODER
199
TABLE 01
TABLE 02
TABLE 03
80h EN
80h EN
80h EN
MON LOOK-UP
TABLE CONTROL
R0 LOOK-UP
R1 LOOK-UP
SEL 8Fh
TABLE
TABLE
SEL C7h
SEL C7h
F0h
F0h
RESERVED
RESERVED
FFh
FFh
MEMORY PARTITION WITH ADEN BIT = 0
Figure 2. Memory Organization, ADEN = 0
Variable Resistors
The value of each variable resistor is determined by
a temperature-addressed look-up table, which can
assign a unique value (00h to FFh) to each resistor for
every 2°C increment over the -40°C to +102°C range
(see Table 3). See the Temperature Conversion section
for more information.
The variable resistors can also be used in manual
mode. If the TEN bit equals 0, the resistors are in manu-
al mode and the temperature indexing is disabled. The
user sets the resistors in manual mode by writing to
addresses 82h and 83h in Table 01 to control resistors
0 and 1, respectively.
Memory Description
Main and auxiliary memories can be accessed by two
separate device addresses. The Main Device address
is A2h (or value in Table 01 byte 8Ch, when ADFIX = 1)
and the Auxiliary Device address is A0h. A user option
is provided to respond to one or two device addresses.
This feature can be used to save component count in
SFF applications (Main Device address can be used)
or other applications where both GBIC (Auxiliary
Device address can be used) and monitoring functions
are implemented and two device addresses are need-
ed. The memory blocks are enabled with the corre-
sponding device address. Memory space from 80h and
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