MAX8751 查看數據表（PDF） - Maxim Integrated

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MAX8751

Fixed-Frequency, Full-Bridge CCFL Inverter Controller

Maxim Integrated 

Fixed-Frequency, Full-Bridge CCFL

Inverter Controller

Pin Description

PIN

NAME

FUNCTION

Transformer Secondary Voltage-Feedback Input. VFB pin sets secondary overvoltage limit by using a

capacitive voltage-divider between the high voltage of the CCFL lamp and GND. When the peak

1

VFB

voltage on VFB exceeds the internal overvoltage threshold, the controller turns on an internal current

sink, discharging the COMP capacitor, limiting the secondary voltage. See the Transformer

Secondary Voltage Limiting section for details.

Fault Timer-Adjustment Pin. A fault condition sets an internal current source to charge a capacitor

2

TFLT

connected between TFLT and GND. Connect a capacitor from TFLT to GND to set the timeout period

for open-lamp fault and secondary short-circuit faults. See the Lamp-Out Protection section for

details.

Brightness Control Input. The usable brightness control range is from 0 to 2V. VCNTL = 0 represents

3

CNTL

minimum brightness (10% DPWM duty cycle), VCNTL = 2V represents full brightness (100% DPWM

duty cycle). When VCNTL is between 2V and 3V, the brightness is still 100%. The MAX8751 enters into

slave mode when CNTL is connected to VCC. See the DPWM Dimming Control section for details.

4

SHDN Shutdown Control Input. The MAX8751 shuts down when SHDN is pulled to GND.

5

LSYNC DPWM Sync Input. DPWM frequency can be synchronized with an external signal on LSYNC. When

SEL is connected to VCC, the duty cycle of the LSYNC signal determines the brightness.

6

LFCK

Internal DPWM Oscillator Clock Output. LFCK becomes a logic-level input when CNTL is connected

to VCC.

7

DPWM DPWM Signal Output. The DPWM output is used to control the DPWM frequency of the slave IC in

master-slave operation. See the Slave Operation (HFCK, LFCK, PSCK, DPWM) section for details.

8

PSCK

Phase-Shift Clock Output. See the Slave Operation (HFCK, LFCK, PSCK, DPWM) and Phase Shift

(PS1, PS2) sections for details.

9

HFCK Main Switching Oscillator Clock Output. HFCK is a logic-level input when CNTL is connected to VCC.

10

HSYNC Main Switching Frequency Sync Input. Switching frequency can be synchronized with an external

signal on HSYNC.

Brightness Control Select Input. Brightness can be adjusted with an analog voltage on CNTL or with

11

SEL

an external sync signal. Connecting SEL to VCC enables analog control input. Connect SEL to VCC to

enable brightness control using external sync signal.

Frequency Adjustment Pin for Internal DPWM Oscillator. Connect a resistor from LF to GND to set the

12

LF

internal DPWM oscillator frequency. fDPWM = 208Hz × 150kΩ / RLF. LF becomes a logic-level input

when CNTL is connected to VCC. See the DPWM Dimming Control section for details.

Frequency Adjustment Pin for Main Switching Oscillator. Connect a resistor from HF to GND to set the

13

HF

main oscillator frequency. fSW = 54kHz × 100kΩ / RHF. HF is a logic-level input when CNTL is

connected to VCC.

14

PS1

Phase-Shift Select Input for Slave. For details, see the Slave Operation (HFCK, LFCK, PSCK, DPWM)

section.

15

PGND2 Power Ground. PGND is the return for the GL2 gate driver.

16

GL2

Gate-Driver Output for Low-Side MOSFET NL2

17

BST2

High-Side Gate Driver GH2 Supply Input. The MAX8751 includes an integrated boost diode. Connect

a 0.1µF capacitor between LX2 and BST2 to complete the bootstrap circuit.

10 ______________________________________________________________________________________

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