MAX4533CAP View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX4533CAP

Quad, Rail-to-Rail, Fault-Protected, SPDT Analog Switch

Maxim Integrated 

Quad, Rail-to-Rail, Fault-Protected,

SPDT Analog Switch

Table 1. Switch States in Normal and Fault Conditions

POWER

SUPPLIES

(V+, V-)

INPUT

RANGE

NC_

NO_

On

Between Rails

On

Off

On

Between Rails

Off

On

On

Between V+ and (+40V - V+)

On

Off

On

Between V+ and (+40V - V+)

Off

On

On

Between V- and (-40V - V-)

On

Off

On

Between V- and (-40V - V-)

Off

On

Off

Between Rails

Off

Off

OUTPUT

NC_

NO_

V+

V+

V-

V-

Follows the load

terminal voltage.

Failure Modes

The MAX4533 is not a lightning arrester or surge pro-

tector. Exceeding the fault-protection voltage limits on

NO_ or NC_, even for very short periods, can cause the

device to fail.

Applications Information

Ground

There is no connection between the analog signal

paths and GND. The analog signal paths consist of an

N-channel and P-channel MOSFET with their sources

and drains paralleled and their gates driven out of

phase to V+ and V- by the logic-level translators.

V+ and GND power the internal logic and logic-level

translators and set the input logic thresholds. The logic-

level translators convert the logic levels to switched V+

and V- signals to drive the gates of the switches. This

drive signal is the only connection between the power

supplies and the analog signals. GND, IN_, and COM_

have ESD protection diodes to V+ and V-.

Supply Current Reduction

When the logic signals are driven rail-to-rail from 0 to

+12V or -15V to +15V, the supply current reduces to

approximately half of the supply current when the logic

input levels are at 0 to 5V.

Power Supplies

The MAX4533 operates with bipolar supplies between

±4.5V and ±18V. The V+ and V- supplies need not be

symmetrical, but their difference can not exceed the

absolute maximum rating of +44V. The MAX4533 oper-

ates from a single supply between +9V and +36V when

V- is connected to GND.

Test Circuits/Timing Diagrams

3V

VIN

0V

+10V

VCOM 0V

-10V

tOFF

tR < 20ns

tF < 20ns

50%

tOFF

tOPEN

50%

50%

tON

50%

tON

50%

50%

tOPEN

MAX4533

+10V

NC_

-10V

NO_

IN_

LOGIC

INPUT

V+

GND

+15V

SWITCH OUTPUT

COM_

2kΩ

V-

-15V

(REPEAT TEST FOR IN2, IN3, AND IN4.)

Figure 2. Switching-Time Test Circuit

10 ______________________________________________________________________________________

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