AD538AD(RevC) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD538AD Datasheet PDF : 11 Pages
| |||
AD538
ANALOG COMPUTATION OF POWERS AND ROOTS
It is often necessary to raise the quotient of two input signals to
a power or take a root. This could be squaring, cubing, square-
rooting or exponentiation to some noninteger power. Examples
include power series generation. With the AD538, only one or
two external resistors are required to set ANY desired power,
over the range of 0.2 to 5. Raising the basic quantity VZ /VX to a
power greater than one requires that the gain of the AD538’s log
ratio subtractor be increased, via an external resistor between
pins A and D. Similarly, a voltage divider that attenuates the log
ratio output between points B and C will program the power to
a value less than one.
RA
B
C
A
D
3
12
18
17
POWERS
VZ
2
VY
10
VY
(
VZ
VREF
)m
15
8
VO
m RA
2 196⍀
3 97.6⍀
4 64.9⍀
5 48.7⍀
VREF
VX
RA
=
196⍀
M –1
RB = RC Յ 200⍀
RB
RC
B
C
3
12
VZ
2
VY
10
VY
(
VZ
VREF
)m
15
8
VO
ROOTS
m
RB
1/2 100⍀
1/3 100⍀
1/4 150⍀
1/5 162⍀
RC
100⍀
49.9⍀
49.9⍀
40.2⍀
VREF
VX
RB
RC
=
1
M
–1
Figure 15. Basic Configurations and Transfer Functions
for the AD538
SQUARE ROOT OPERATION
The explicit square root circuit of Figure 16 illustrates a precise
method for performing a real-time square root computation. For
added flexibility and accuracy, this circuit has a scale factor
adjustment.
The actual square rooting operation is performed in this circuit
by raising the quantity VZ / VX to the one-half power via the
resistor divider network consisting of resistors RB and RC. For
maximum linearity, the two resistors should be 1% (or better)
ratio-matched metal film types.
One volt scaling is achieved by dividing-down the 2 V reference
and applying approximately 1 V to both the VY and VX inputs.
In this circuit, the VX input is intentionally set low, to about
0.95 V, so that the VY input can be adjusted high, permitting a
± 5% scale factor trim. Using this trim scheme, the output volt-
age will be within ± 3 mV ± 0.2% of the ideal value over a 10 V
to 1 mV input range (80 dB). For a decreased input dynamic
range of 10 mV to 10 V (60 dB) the error is even less; here the
output will be within ± 2 mV ± 0.2% of the ideal value. The
bandwidth of the AD538 square root circuit is approximately
280 kHz with a 1 V p-p sine wave with a +2 V dc offset.
This basic circuit may also be used to compute the cube, fourth
or fifth roots of an input waveform. All that is required for a
given root is that the correct ratio of resistors, RC and RB, be
selected such that their sum is between 150 Ω and 200 Ω.
The optional absolute value circuit shown preceding the AD538
allows the use of bipolar input voltages. Only one op amp is
required for the absolute value function because the IZ input of
the AD538 functions as a summing junction. If it is necessary to
preserve the sign of the input voltage, the polarity of the op amp
output may be sensed and used after the computation to switch
the sign bit of a D.V.M. chip.
VOUT = 1V
VIN
1V
OPTIONAL
ABSOLUTE VALUE SECTION
5k⍀
10k⍀
20k⍀
IN4148 IN4148
IZ
1
VZ 2 25k⍀
LOG
RATIO
18 A
17 D
RB
100⍀
*
+VS
7
20k⍀ VOS
VIN
20k⍀ 2 1
8
6
3
AD OP-07
4 OR AD611
–VS
(VOS TAP
TO –VS)
B
3
+10V
4
+2V
+2V
5
+15V 6
100⍀
INTERNAL
VOLTAGE
REFERENCE
100⍀
AD538
16 IX
VX
15
25k⍀ SIGNAL
GND
14
PWR
GND
13
VOUT
1k⍀
100⍀
SCALE FACTOR
TRIM
1k⍀
–15V 7
VO
8
OUTPUT
25k⍀
I9
ANTILOG
LOG
12 C
IY
11
VY
10
25k⍀
D1
IN4148
*RATIO MATCH 1% METAL FILM
RESISTORS FOR BEST ACCURACY
RC
100⍀
*
Figure 16. Square Root Circuit
REV. C
–9–
Share Link: 