AD9840AJSTZRL View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9840AJSTZRL

Complete 10-Bit 40 MSPS CCD Signal Processor

Analog Devices 

AD9840A

CCD

VOUT

V-DRIVE

BUFFER

0.1␮F

AD9840A

CCDIN

ADCOUT

REGISTER

DATA

DIGITAL

OUTPUTS

SERIAL

INTERFACE

CCD

TIMING

CDS/CLAMP

TIMING

TIMING

GENERATOR

DIGITAL IMAGE

PROCESSING

ASIC

Figure 16. System Applications Diagram

APPLICATIONS INFORMATION

The AD9840A is a complete Analog Front End (AFE) product

for digital still camera and camcorder applications. As shown in

Figure 16, the CCD image (pixel) data is buffered and sent to

the AD9840A analog input through a series input capacitor. The

AD9840A performs the dc restoration, CDS, gain adjustment,

black level correction, and analog-to-digital conversion. The

AD9840A’s digital output data is then processed by the image

processing ASIC. The internal registers of the AD9840A—used

to control gain, offset level, and other functions—are programmed

by the ASIC or microprocessor through a 3-wire serial digital

interface. A system timing generator provides the clock signals

for both the CCD and the AFE.

Internal Power-On Reset Circuitry

After power-on, the AD9840A will automatically reset all internal

registers and perform internal calibration procedures. This takes

approximately 1 ms to complete. During this time, normal clock

signals and serial write operations may occur. However, serial

register writes will be ignored until the internal reset operation is

completed. Pin 43 (formerly RSTB on the AD9843 non-A) is no

longer used for the reset operation. Toggling Pin 43 in the

AD9840A will have no effect.

Grounding and Decoupling Recommendations

As shown in Figure 17, a single ground plane is recommended

for the AD9840A. This ground plane should be as continuous

as possible, particularly around Pins 25 through 39. This will

ensure that all analog decoupling capacitors provide the lowest

possible impedance path between the power and bypass pins

and their respective ground pins. All decoupling capacitors

should be located as close as possible to the package pins. A

single clean power supply is recommended for the AD9840A,

but a separate digital driver supply may be used for DRVDD

(Pin 13). DRVDD should always be decoupled to DRVSS (Pin

14), which should be connected to the analog ground plane.

Advantages of using a separate digital driver supply include

using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC,

reducing digital power dissipation, and reducing potential noise

coupling. If the digital outputs (Pins 3–12) must drive a load

larger than 20 pF, buffering is recommended to reduce digital

code transition noise. Alternatively, placing series resistors

close to the digital output pins may help reduce noise.

–14–

REV. 0

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