ADSP-2187NBSTZ-320 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-2187NBSTZ-320 Datasheet PDF : 48 Pages
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such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, ADSP-218xN series members
remain in the idle state for up to a maximum of n processor
cycles (n = 16, 32, 64, or 128) before resuming nor-
mal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
ADSP-218xN
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-218xN series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xN series members also provide four external inter-
rupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
1/2 ؋ CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
FULL MEMORY MODE
ADSP-218xN
CLKIN
XTAL
ADDR13–0 14
FL0–2
A13–0
D23–16 A0–A21
1/2 ؋ CLOCK
OR
CRYSTAL
IRQ2/PF7
24
IRQE/PF4 DATA23–0
D15–8
DATA
BYTE
MEMORY
IRQL0/PF5
IRQL1/PF6
BMS
CS
WR
A10–0
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT0
RD
IOMS
DPMMSSInsert
CMS
systDADem212333–––i008nterfDADACaADADScTDTDeAARRdia2g(0Pr4EOaM8TI/RmVOWELIEPOMOSRHhCOPL8EeAARAKRrTCYeYAIEOLNSS)
PM SEGMENTS
TWO 8K
DM SEGMENTS
SCLK0
BR
RFS0
BG
TFS0
BGH
DT0
PWD
DR0
PWDACK
SERIAL
DEVICE
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
µCONTROLLER
HOST MEMORY MODE
ADSP-218xN
CLKIN
XTAL
FL0–2
1
A0
IRQ2/PF7
16
IRQE/PF4 DATA23–8
IRQL0/PF5
IRQL1/PF6
BMS
MODE D/PF3
WR
MODE C/PF2
MODE A/PF0
RD
MODE B/PF1
SPORT1
IOMS
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
PMS
SPORT0
SCLK0
RFS0
TFS0
DT0
DMS
CMS
BR
BG
DR0
BGH
IDMA PORT
PWD
IRD/D6
PWDACK
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15-0
16
Figure 2. Basic System Interface
Rev. A | Page 7 of 48 | August 2006
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