ADSP-2188NBSTZ-320 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-2188NBSTZ-320 Datasheet PDF : 48 Pages
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ADSP-218xN
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
Parameter1
Min
Max
Unit
Timing Requirements:
tIKR
IACK Low Before Start of Read2
tIRP
Duration of Read3
Switching Characteristics:
0
ns
10
ns
tIKHR
IACK High After Start of Read2
tIKDH
IAD15–0 Previous Data Hold After End of Read3
tIKDD
IAD15–0 Previous Data Disabled After End of Read3
tIRDE
IAD15–0 Previous Data Enabled After Start of Read
tIRDV
IAD15–0 Previous Data Valid After Start of Read
10
ns
0
ns
10
ns
0
ns
10
ns
1 Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register
or by an external host writing to the register. Disabled by default.
2 Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3 End of Read = IS High or IRD High.
IACK
IS
tIK R
tIK H R
IRD
tIR P
tIR D E
IAD15–0
PR E V IO U S
DATA
tIR D V
L EG EN D :
IM PL IES TH A T IS A N D IR D C A N B E
HELD INDEFINITELY BY HO ST
tIK D H
tIK D D
Figure 37. IDMA Read, Short Read Cycle in Short Read Only Mode
Rev. A | Page 39 of 48 | August 2006
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