ADSP-218xN
Memory Write
Table 19. Memory Write
Parameter
Switching Characteristics:
tDW
Data Setup before WR High1
tDH
Data Hold after WR High
tWP
WR Pulse Width
tWDE
WR Low to Data Enabled
tASW
A13–0, xMS Setup before WR Low2
tDDR
Data Disable before WR or RD Low
tCWR
CLKOUT High to WR Low
tAW
A13–0, xMS Setup before WR Deasserted
tWRA
A13–0, xMS Hold after WR Deasserted
tWWR
WR High to RD or WR Low
1 w = wait states 3 tCK.
2 xMS = PMS, DMS, CMS, IOMS, BMS.
Min
Max
0.5tCK– 4 + w
0.25tCK – 1
0.5tCK – 3 + w
0
0.25tCK – 3
0.25tCK – 3
0.25tCK – 2
0.75tCK – 5 + w
0.25tCK – 1
0.5tCK – 3
0.25tCK + 4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
ADDRESS LINES1
DMS, PMS,
BMS, CMS,
IOMS
WR
DATA LINES2
RD
tWRA
tASW
tCWR
tWP
tAW
tDW
tWDE
tWWR
tDH
tDDR
1ADDRESS LINES FOR ACCESSES ARE:
BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs)
I/O SPACE: A10–0
EXTERNAL PM AND DM: A13–0
2DATA LINES FOR ACCESSES ARE:
BDMA: D15–8
I/O SPACE: D23–8
EXTERNAL DM: D23–8
EXTERNAL PM: D23–0
Figure 30. Memory Write
Rev. A | Page 32 of 48 | August 2006