ADSP-2187NBSTZ-320 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-2187NBSTZ-320 Datasheet PDF : 48 Pages
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ADSP-218xN
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is only 16 bits wide.
Table 4. PMOVLAY Bits
Processor
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
All Processors
All Processors
PMOVLAY
Memory
No Internal Overlay Not Applicable
Region
0
Internal Overlay
No Internal Overlay Not Applicable
Region
0, 4, 5
Internal Overlay
0, 4, 5, 6, 7
Internal Overlay
0, 4, 5
Internal Overlay
1
External Overlay 1
2
External Overlay 2
A13
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
0
1
A12 – 0
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
13 LSBs of Address Between 0x2000 and 0x3FFF
13 LSBs of Address Between 0x2000 and 0x3FFF
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used
for the storage of data variables and for memory-mapped con-
trol registers. The ADSP-218xN series has up to 56K words of
Data Memory RAM on-chip. Part of this space is used by 32
memory-mapped registers. Support also exists for up to two 8K
external memory overlay spaces through the external data bus.
All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register and the wait state mode bit.
Data Memory (Host Mode) allows access to all internal mem-
ory. External overlay access is limited by a single external
address line (A0).
Table 5. DMOVLAY Bits
Processor
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
All Processors
DMOVLAY
No Internal Overlay Region
0
No Internal Overlay Region
0, 4, 5
0, 4, 5, 6, 7, 8
0, 4, 5, 6, 7
1
Memory
Not Applicable
Internal Overlay
Not Applicable
Internal Overlay
Internal Overlay
Internal Overlay
External Overlay 1
All Processors 2
External Overlay 2
A13
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
0
1
A12 – 0
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
13 LSBs of Address
Between 0x0000 and
0x1FFF
13 LSBs of Address
Between 0x0000 and
0x1FFF
Memory-Mapped Registers (New to the ADSP-218xM and
N series)
ADSP-218xN series members have three memory-mapped reg-
isters that differ from other ADSP-21xx Family DSPs. The slight
modifications to these registers (Wait State Control, Program-
mable Flag and Composite Select Control, and System Control)
provide the ADSP-218xN’s wait state and BMS control features.
Default bit values at reset are shown; if no value is shown, the bit
is undefined at reset. Reserved bits are shown on a grey field.
These bits should always be written with zeros.
I/O Space (Full Memory Mode)
ADSP-218xN series members support an additional external
memory space called I/O space. This space is designed to sup-
port simple connections to peripherals (such as data converters
and external registers) or to bus interface ASIC data registers.
I/O space supports 2048 locations of 16-bit wide data. The lower
eleven bits of the external address bus are used; the upper three
bits are undefined.
Two instructions were added to the core ADSP-2100 Family
instruction set to read from and write to I/O memory space. The
I/O space also has four dedicated three-bit wait state registers,
Rev. A | Page 11 of 48 | August 2006
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