AD679BJ(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD679BJ
(Rev.:RevD)

14-bit 128 kSPS complete sampling ADC

Analog Devices 

AD679

and digital ground planes are also desirable, with a single inter-

connection point to minimize ground loops. Analog signals

should be routed as far as possible from digital signals and

should cross them at right angles.

The AD679 incorporates several features to help the user’s lay-

out. Analog pins (VEE, AIN, AGND, REFOUT, REFIN, BIPOFF,

VCC) are adjacent to help isolate analog from digital signals. In

addition, the 10 MΩ input impedance of AIN minimizes input

trace impedance errors. Finally, ground currents have been

minimized by careful circuit architecture. Current through

AGND is 200 µA, with no code dependent variation. The cur-

rent through DGND is dominated by the return current for

DB7–DB0 and EOC.

Figure 7 shows the use of the AD586 with the AD679 in a bipolar

input mode. Over the 0°C to 70°C range, the AD586 L-grade

exhibits less than a 2.25 mV output change from its initial value

at 25°C. REFIN (Pin 9) scales its input by a factor of two; thus,

this change becomes effectively 4.5 mV. When applied to the

AD679, this results in a total gain drift of 0.09% FSR, which is

an improvement over the on-chip reference performance of

0.11% FSR. A noise-reduction capacitor, CN, has been shown.

This capacitor reduces the broadband noise of the AD586 out-

put, thereby optimizing the overall ac and dc performance of the

AD679.

SUPPLY DECOUPLING

The AD679 power supplies should be well filtered, well regu-

lated, and free from high frequency noise. Switching power sup-

plies are not recommended due to their tendency to generate

spikes that can induce noise in the analog system.

Decoupling capacitors should be used in very close layout prox-

imity between all power supply pins and analog ground. A 10 µF

tantalum capacitor in parallel with a 0.1 µF ceramic capacitor

provides adequate decoupling.

An effort should be made to minimize the trace length between

the capacitor leads and the respective converter power supply

and common pins. The circuit layout should attempt to locate

the AD679, associated analog input circuitry, and interconnec-

tions as far as possible from logic circuitry. A solid analog

ground plane around the AD679 isolates large switching ground

currents. For these reasons, the use of wire wrap circuit con-

struction is not recommended; careful printed circuit construc-

tion is preferred.

GROUNDING

If a single AD679 is used with separate analog and digital

ground planes, connect the analog ground plane to AGND and

the digital ground plane to DGND, keeping lead lengths as

short as possible. Then connect AGND and DGND together at

the AD679. If multiple AD679s are used or if the AD679 shares

analog supplies with other components, connect the analog and

digital returns together once at the power supplies rather than at

each chip. This prevents large ground loops, which inductively

couple noise and allow digital currents to flow through the ana-

log system.

USE OF EXTERNAL VOLTAGE REFERENCE

The AD679 features an on-chip voltage reference. For improved

gain accuracy over temperature, a high performance external

voltage reference may be used in place of the on-chip reference.

The AD586 and AD588 are popular references appropriate for

use with high resolution converters. The AD586 is a low cost

reference that utilizes a buried Zener architecture to provide low

noise and drift. The AD588 is a higher performance reference

that uses a proprietary implanted buried Zener diode in con-

junction with laser-trimmed thin-film resistors for low offset and

low drift.

Figure 7. Bipolar Input with Gain and Offset Trims

Figure 8 shows the AD679 in unipolar input mode with the

AD588 reference. The AD588 output is accurate to 0.65 mV

from its value at 25°C over the 0°C to 70°C range. This results

in a 0.06% FSR total gain drift for the AD679, a substantial im-

provement over the on-chip reference performance of 0.11%

FSR. A noise-reduction network on Pins 4, 6, and 7 has been

shown. The 1 µF capacitors form low-pass filters with the inter-

nal resistance of the AD588 Zener and amplifier cells and exter-

nal resistance. This reduces the high frequency (to 1 MHz)

noise of the AD588, providing optimum ac and dc performance

of the AD679.

REFIN

Figure 8. Unipolar Input with Gain and Offset Trims

REV. D

–11–

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