AD7837ARR View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD7837ARR

LC2MOS Complete, Dual 12-Bit MDACs

Analog Devices 

AD7837/AD7847–SPECIFICATIONS1

(VDD = +15 V ؎ 5%, VSS = –15 V ؎ 5%, AGNDA = AGNDB = DGND

= O V. VREFA = VREFB = +10 V, RL = 2 k⍀, CL = 100 pF [VOUT connected to RFB AD7837]. All specifications TMIN to TMAX unless otherwise noted.)

Parameter

A Version

B Version S Version

Units

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

12

Relative Accuracy2

±1

Differential Nonlinearity2

±1

Zero Code Offset Error2

@ +25°C

±2

TMIN to TMAX

±4

Gain Error2

@ +25°C

±4

TMIN to TMAX

±5

12

12

± 1/2

±1

±1

±1

±2

±2

±3

±4

±2

±4

±3

±5

Bits

LSB max

LSB max

mV max

mV max

LSB max

LSB max

Guaranteed Monotonic

DAC Latch Loaded with All 0s

Temperature Coefficient = ± 5 µV/°C typ

DAC Latch Loaded with All 1s

Temperature Coefficient = ± 2 ppm of

FSR/°C typ

REFERENCE INPUTS

VREF Input Resistance

8/13

VREFA, VREFB Resistance Matching ± 2

DIGITAL INPUTS

Input High Voltage, VINH

2.4

Input Low Voltage, VINL

0.8

Input Current

±1

Input Capacitance3

8

8/13

8/13

±2

±2

2.4

2.4

0.8

0.8

±1

±1

8

8

kΩ min/max

% max

Typical Input Resistance = 10 kΩ

Typically ± 0.25%

V min

V max

µA max

pF max

Digital Inputs at 0 V and VDD

ANALOG OUTPUTS

DC Output Impedance

Short Circuit Current

POWER REQUIREMENTS4

VDD Range

VSS Range

Power Supply Rejection

∆Gain/∆VDD

∆Gain/∆VSS

IDD

ISS

0.2

0.2

0.2

Ω typ

11

11

11

mA typ

VOUT Connected to AGND

14.25/15.75 14.25/15.75 14.25/15.75 V min/max

–14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/max

± 0.01

± 0.01

8

6

± 0.01

± 0.01

8

6

± 0.01

± 0.01

8

6

% per % max

% per % max

mA max

mA max

VDD = 15 V ± 5%, VREF = –10 V

VSS = –15 V ± 5%, VREF = +10 V

Outputs Unloaded. Inputs at Thresholds.

Typically 5 mA

Outputs Unloaded. Inputs at Thresholds.

Typically 3 mA

AC CHARACTERISTICS2, 3

Voltage Output Settling Time

3

5

Slew Rate

11

Digital-to-Analog Glitch Impulse 10

Channel-to-Channel Isolation

VREFA to VOUTB

–95

VREFB to VOUTA

–95

Multiplying Feedthrough Error

–90

Unity Gain Small Signal BW

750

Full Power BW

175

Total Harmonic Distortion

–88

Digital Crosstalk

1

Output Noise Voltage @ +25°C

(0.1 Hz to 10 Hz)

2

Digital Feedthrough

1

3

3

5

5

11

11

10

10

–95

–95

–95

–95

–90

–90

750

750

175

175

–88

–88

1

1

2

2

1

1

µs typ

µs max

V/µs typ

nV secs typ

dB typ

dB typ

dB typ

kHz typ

kHz typ

dB typ

nV secs typ

µV rms typ

nV secs typ

Settling Time to Within ± 1/2 LSB of Final

Value. DAC Latch Alternately Loaded

with All 0s and All 1s

1 LSB Change Around Major Carry

VREFA = 20 V p-p, 10 kHz Sine Wave.

DAC Latches Loaded with All 0s

VREFB = 20 V p-p, 10 kHz Sine Wave.

DAC Latches Loaded with All 0s

VREF = 20 V p-p, 10 kHz Sine Wave.

DAC Latch Loaded with All 0s

VREF = 100 mV p-p Sine Wave. DAC

Latch Loaded with All 1s

VREF = 20 V p-p Sine Wave. DAC

Latch Loaded with All 1s

VREF = 6 V rms, 1 kHz. DAC Latch

Loaded with All 1s

Code Transition from All 0s to All 1s and

Vice Versa

See Typical Performance Graphs

Amplifier Noise and Johnson Noise of RFB

NOTES

1Temperature ranges are as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.

2See Terminology.

3Guaranteed by design and characterization, not production tested.

4The Devices are functional with VDD/VSS = ± 12 V (See typical performance graphs.).

Specifications subject to change without notice.

–2–

REV. C

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