ADP3333ARM-3.15 View Datasheet(PDF) - Analog Devices
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ADP3333ARM-3.15 Datasheet PDF : 8 Pages
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ADP3333
THEORY OF OPERATION
The new anyCAP LDO ADP3333 uses a single control loop for
regulation and reference functions see (Figure 2). The output
voltage is sensed by a resistive voltage divider consisting of R1
and R2 which is varied to provide the available output voltage
option. Feedback is taken from this network by way of a series
diode (D1) and a second resistor divider (R3 and R4) to the
input of an amplifier.
INPUT
OUTPUT
ATTENUATION
Q1
(VBANDGAP /VOUT)
COMPENSATION
R1
CAPACITOR
NONINVERTING
WIDEBAND
gm
DRIVER
ADP3333
PTAT
VOS
R3 D1
FB (a)
PTAT
R4 CURRENT
R2
CLOAD
RLOAD
GND
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it pro-
duces a large, temperature-proportional input “offset voltage” that
is repeatable and very well controlled. The temperature propor-
tional offset voltage is combined with the complementary diode
voltage to form a “virtual bandgap” voltage, implicit in the network,
although it never appears explicitly in the circuit. Ultimately, this
patented design makes it possible to control the loop with only one
amplifier. This technique also improves the noise characteristics
of the amplifier by providing more flexibility on the trade-off of
noise sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the load-
ing of the divider so that the error resulting from base current
loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to include
the load capacitor in a pole splitting arrangement to achieve
reduced sensitivity to the value, type and ESR of the load
capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. Moreover,
the ESR value, required to keep conventional LDOs stable, changes
depending on load and temperature. These ESR limitations make
designing with LDOs more difficult because of their unclear
specifications and extreme variations over temperature.
With the ADP3333 anyCAP LDO, this is no longer true. It can be
used with virtually any good quality capacitor, with no constraint
on the minimum ESR. This innovative design allows the circuit to
be stable with just a small 1 µF capacitor on the output. Additional
advantages of the pole splitting scheme include superior line noise
rejection and very high regulator gain which leads to excellent line
and load regulation. An impressive ±1.8% accuracy is guaranteed
over line, load and temperature.
Additional features of the circuit include current limit and ther-
mal shutdown.
APPLICATION INFORMATION
Capacitor Selection
Output Capacitor
The stability and transient response of the LDO is a function of
the output capacitor. The ADP3333 is stable with a wide range
of capacitor values, types and ESR (anyCAP). A capacitor as
low as 1.0 µF is all that is needed for stability; larger capacitors
can be used if high current surges on the output are anticipated.
The ADP3333 is stable with extremely low ESR capacitors
(ESR » 0), such as Multilayer Ceramic Capacitors (MLCC) or
OSCON. Note that the effective capacitance of some capacitor
types fall below the minimum over temperature or with dc voltage.
Ensure that the capacitor provides at least 1.0 µF of capacitance
over temperature and dc bias.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but it is recom-
mended in any application involving long input wires or high
source impedance. Connecting a 1.0 µF capacitor from the input
to ground reduces the circuit's sensitivity to PC board layout and
input transients. If a larger output capacitor is necessary then a
larger value input capacitor is also recommended.
Output Current Limit
The ADP3333 is short circuit protected by limiting the pass
transistor’s base drive current. The maximum output current is
limited to about 1 A. See TPC 14.
Thermal Overload Protection
The ADP3333 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit. Thermal
protection limits the die temperature to a maximum of 165°C.
Under extreme conditions (i.e., high ambient temperature and
power dissipation) where the die temperature starts to rise above
165°C, the output current will be reduced until the die tempera-
ture has dropped to a safe level.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device's power dissipation should be externally
limited so that the junction temperature will not exceed 125°C.
–6–
REV. 0
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