AT90CAN128-UL View Datasheet(PDF) - Atmel Corporation
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AT90CAN128-UL Datasheet PDF : 413 Pages
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CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must
ensure that a sufficient division factor is chosen if the selected clock source has a higher
frequency than the maximum frequency of the device at the present operating condi-
tions. The device is shipped with the CKDIV8 Fuse programmed.
Table 16. Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
1
2
4
8
16
32
64
128
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note:
When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock
only. The frequency of the asynchronous clock must be lower than 1/4th of the frequency
of the scaled down Source clock. Otherwise, interrupts may be lost, and accessing the
Timer/Counter0 registers may fail.
42 AT90CAN128
4250E–CAN–12/04
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