WT6014 View Datasheet(PDF) - Weltrend Semiconductor
Part Name
Description
Manufacturer
WT6014 Datasheet PDF : 19 Pages
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FUNCTIONAL DESCRIPTION
WT6014
Digital Monitor Controller
Ver. 1.21 Jul-31-1998
CPU
The CPU core is 6502 compatible, operating frequency is 4MHz. Address bus is 16-bit and data bus is
8-bit. the non-maskable interrupt (/NMI) of 6502 is changed to maskable interrupt and is defined as
the INT0. The interrupt request (/IRQ) of 6502 is defined as the INT1.
The initial stack pointer is 00FFH, because page 1 and page 0 are mapped to same area.
Please refer the 6502 reference menu for more detail.
ROM
4096 bytes maskable ROM is provided for program codes.
Address is located from F000H to FFFFH.
The following addresses are reserved for special purpose :
FFFAH (low byte) and FFFBH (high byte) : INT0 interrupt vector.
FFFCH (low byte) and FFFDH (high byte) : program reset vector.
FFFEH (low byte) and FFFFH (high byte) : INT1 interrupt vector.
RAM
Built-in 128 bytes SRAM, address is located from 0080H to 00FFH
0000H
:
001CH
REGISTERS
001DH
:
007FH
Reserved
0080H
:
00FFH
RAM
0100H
: Page 1 mapped to Page 0
01FFH
0200H
:
EFFFH
Reserved
F000H
:
:
:
FFFFH
ROM
Low VDD Voltage Reset
A VDD voltage detector is built inside the chip. When VDD is below 4.0 volts, the whole chip will be
reset just like power-on-reset.
Note that the 4.0 volts varies with temperature and process. Please refer the electrical characteristics.
Weltrend Semiconductor, Inc.
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