Interrupt Control
WT6014
Digital Monitor Controller
Ver. 1.21 Jul-31-1998
There are two interrupt sources : INT0 and INT1. INT0 has the higher priority.
Interrupt vector :
INT0 : FFFAH (low byte) and FFFBH (high byte).
INT1 : FFFEH (low byte) and FFFFH (high byte).
INT0 occurs when :
(1) data buffer empty in the DDC1 mode (DDC="1" and DDC2B="0").
(2) acknowledge or STOP condition is detected in the DDC2B mode (DDC="1" and DDC2B="0").
INT1 occurs when :
(1) a falling edge or a low level occurs on the /IRQ pin (EXT="1").
(2) the timer is time out (TIM="1").
(3) SYNC processor has a valid frequency (SYNC="1").
If H/V ="0" , it is vertical frequency ready.
If H/V ="1" , it is horizontal frequency ready.
INT0 is cleared when :
(1) writing the REG#18H in DDC1 state.
(2) writing the REG#19H in DDC2B state.
INT1 is cleared when :
(1) reading the REG#1AH if EXT="1".
(2) reading the REG#1BH if TIM="1".
(3) reading the REG#16H if SYNC="1".
IEN_D
DDC
4MHz
IEN_X
IRQ
IEN_T
TOUT
IEN_S
FRDY
D
Q
CK Q
INT0
INT1
Weltrend Semiconductor, Inc.
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