5962F0252302QXX View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962F0252302QXX

Microcontroller

Aeroflex UTMC 

1.27 Advanced Read/Write Signal (ADV_RD_WR)

The UT80CRH196KDS provides an early indication of an

external memory cycle direction being a read or write. This

signal is output on pin 2. See Table 10 and Figure 4 for

description of operation.

1.28 Byte-Wide Reads of the HSI_Time SFR

In order to ensure that the next HSI event is loaded from the

FIFO into the HSI holding register, the HSI_TIME special

function register must be read as a 16-bit word. Byte-wide

reads of the HSI_TIME register will not result in successful

loading of the HSI holding register.

1.29 HOLD Must Be Synchronized with CLKOUT

The DMA arbiter must synchronize the HOLD signal with the

CLKOUT on the UT80CRH196KDS. The timing diagram in

Figure 8 eludes to the synchronicity of the HOLD signal, but

does not clearly identify the outcome if the HOLD signal does

not satisfy the timing parameter tHVCH. If the HOLD setup

time is violated on the industry standard 80CRH196KDS, it

will require one additional CLKOUT cycle before it recog-

nizes the state change of HOLD. Violating the HOLD setup

time on the UT80CRH196KDS will result in a metastable

condition and the UT80CRG196KDS’s reaction is undefined.

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