5962F0252301QXX View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962F0252301QXX

Microcontroller

Aeroflex UTMC 

APPENDIX A

Difference Between Industry Standard and UT80CRH196KDS

1.0 DIFFERENCES TO INDUSTRY

STANDARD 80C196KD

1.1 Analog to Digital Converter

The Analog to Digital Converter will not be implemented in the

UT80CRH196KDS.

1.3 Clocking

The XTAL2 output is not used and the UT80CRH196KDS

expects the input on the XTAL 1 to be a valid digital clock

signal. The clock should be stable before reset is removed or

Power Down mode is exited. In Power Down mode, a small

number of gates will be clocked by the XTAL1 input. The

UT80CRH196KDS XTAL2 has been replaced with a VSS pin.

1.4 CCB Read after Reset

The CCB fetch after Reset will be a normal fetch as if the chosen

bus width is selectable based on the BUSWIDTH input.

Systems with an 8-bit wide interface should tie BUSWIDTH to

ground. Systems that use BUSWIDTH should perform a normal

decode based on the memory configuration of the system. The

Industry Standard 80C196KD treats the CCB fetch as an 8-bit

fetch (driving the upper 8-bits with address 20H) regardless of

the state of BUSWIDTH.

1.5 Internal Program Memory

The UT80CRH196KDS does not have internal program

memory, and pin 2 (EA) will be ignored for choosing between

internal and external program reads. The user may tie this pin

to ground for compatibility reasons, unless EDAC is enabled.

1.6 Ports 3 and 4

Since the UT80CRH196KDS will not have internal program

memory, Ports 3 and 4 will always be used as the multiplexed

Address and Data bus. Therefore, these ports will not be

configured as I/O ports, and the bidirectional port function of

these pins will not be implemented. The pins will only be

configured as Address and bidirectional data pins.

1.7 Built in EDAC

The UT80CRH196KDS incorporates a built in Error Detection

and Correction circuit for external memory reads and writes.

The EDAC can be controlled from an external pin. The external

pin (Pin 37) can be used to enable or disable this feature

interactively. Therefore, different regions of external memory

can be assigned to have EDAC as necessary. Additionally, the

EDAC check bits will be passed through Port 0, which varies

from the industry standard version where Port 0 is an input only

port. You can control the interrupt behavior of the EDAC engine

by setting bits 6 and 5 of the EDAC Control and Status Register

(EDAC_CS). Additionally, reading bit 4 of the EDAC_CS

allows you to determine if a double bit error occurred, and

reading bits 3 through 0 of the EDAC_CS Register tells you

how many single bit errors have been corrected. The EDAC_CS

Register is located at location 15h of HWindow 1.

1.8 Instruction Queue

The instruction queue is eight bytes deep instead of four. The

instruction queue also interfaces to the CPU through a 16-bit

bus. This configuration will speed up the operation of the

UT80CRH196KDS.

1.9 WDT and Prescalar

The WDT can now be disabled through the software. The

disable feature should allow the user flexibility in using the

Watch Dog Timer. The WDT also now has a prescalar which

can slow down the counter by a factor of 2 0 to 27. The prescalar

will give the user extra time between clears of the WDT. The

WDT prescaler (WDT_SCALE) is located at location 0Dh of

HWindow 1.

1.10 Interrupt Priority Levels

An additional level of priority encoding is available to the user.

Every standard interrupt can be programed to a higher level of

priority. All interrupts in the higher priority will maintain their

relative priority, but low priority interrupts can then be

programmed for a higher interrupt priority if necessary. The

interrupt priority register is 16-bits wide, and maps to the

standard interrupts in the same fashion as the INT_MASK and

INT_MASK1 registers. The high byte of the Interrupt Priority

Register (IN_PRI(hi)) is located at 0Bh of HWindow 1, and the

low byte (INT_PRI(lo)) is located at 0Ah of HWindow 1.

1.11 Faster Multiply and Divide

The multiplier and divider have been optimized to perform their

operations in fewer state times than in the current version.

1.12 Instructions State Time Reduction

The CPU has been streamlined for faster execution where

possible. Examples include 1 state reduction for WORD

immediate instructions, 1 state reductions for long indexed

instructions, and state reductions for the BMOV instructions.

1.13 STACK_PNTR implemented as Special Function

Register

The STACK_PNTR has been implemented as a true Special

Function Register instead of in the RAM to allow for quicker

pushes and pops. If the stack is not used, the SFR can be used

for general purpose data storage.

1.14 Timer3

An additional 16-bit timer/counter has been implemented as a

general purpose timer that can be used if Timer1 and Timer 2

are being dedicated to other functional uses. The current value

of Timer3 can be found in locations 0Fh (high byte), and 0Eh

(low byte) of HWindow 1.

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