5962F0252304QXA View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
5962F0252304QXA Datasheet PDF : 41 Pages
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Legend for I/O fields:
TO
TI
CI
TUO
TDO
TUI
= TTL compatible output
= TTL compatible input
= CMOS only input
= TTL compatible output
(internally pulled high)
= TTL compatible output
(internally pulled low)
= TTL compatible input
(internally pulled high)
TDI
TB
TUQ
TUB
TUBS
PWR
GND
= TTL compatible input
(internally pulled low)
= TTL compatible bidirectional
= TTL compatible quasi-bidirectional
(internally pulled high)
= TTL compatible bidirectional
(internally pulled high)
= TTL compatible bidirectional Schmitt
Trigger (internally pulled high)
= +5V (VDD)
= OV (VSS)
QFP Pin# I/O
1
PWR
2
TO
TB
3
TDI
4
TI
TB
5
TI
TB
Table 10: 68-lead Flat Pack Pin Descriptions
Name
Active
Description
VDD
--- Digital supply voltage (+5V). There are 2 VDD pins, both of
which must be connected.
ADV_RD_WR
--- Advanced Read and Write. This pin has multiplexed functional-
ity: coincident with the Address/Data bus multiplexing. When
address information is output on the AD pins, ADV_RD_WR is
output. When data information is on the AD pins, ECB5 is an I/
O. ADV_RD_WR is output high for an external memory read
cycle, and low for an external memory write cycle.
ECB51
-- EDAC Check Bit 5. Asserting the EDACEN pin will cause the
error detection and correction engine to pass the EDAC Check
Bit 5 through pin 2 of the UT80CRH196KDS during the data
phase of an external memory cycle.
NMI
High Non-Maskable Interrupt. A positive transition causes a vector
through the NMI interrupt at location 203Eh. Assert NMI for at
least 1 state time to guarantee acknowledgment by the interrupt
controller.
P0.3
--- Port 0 Pin 3. An input only port pin that is read at location 0Eh
in HWindow 0.
ECB41
--- EDAC Check Bit 4. Asserting the EDACEN pin will cause the
error detection and correction engine to pass the EDAC Check
Bit 4 through pin 4 of the UT80CRH196KDS.
P0.1
--- Port 0 Pin 1. An input only port pin that is read at location 0Eh
in HWindow 0.
ECB31
--- EDAC Check Bit 3. Asserting the EDACEN pin will cause the
error detection and correction engine to pass the EDAC Check
Bit 3 through pin 5 of the UT80CRH196KDS.
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