73M2910L View Datasheet(PDF) - TDK Corporation
Part Name
Description
Manufacturer
73M2910L Datasheet PDF : 35 Pages
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73M2910L
Microcontroller
REGISTER DESCRIPTION
INTERRUPTS
The core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt,
and an HDLC interrupt. An external interrupt and an HDLC interrupt are unique to the 73M2910L. They do not
exist in a normal 8032 product. Previously unused bits in the IE and IP registers are now serving functions for
these additional interrupt sources. The interrupt vector addresses are as follows:
SOURCE
INT) (IE0)
TF0
INT! (IE1)
TF1
RI + TI
TF2 + EXF2
INT@ - ADDED INTERRUPT
HDLC - ADDED INTERRUPT
VECTOR ADDRESS
003H
00BH
013H
01BH
023H
02BH
033H
03BH
The external interrupt sources, INT(2:0), come from dedicated input pins. The apparent polarity of these pins
is individually controlled by bits in a special interrupt direction register, IDIR (address A9). The interrupt pins
INT! and INT) can be either edge or level generated interrupts as indicated by bits 1 and 3 in the TCON
Register (address 88). Pin INT@ is always an edge generated interrupt. A flag is set when a falling transition
(rising if IDIR bit 2 is set) on this pin is detected. This flag is automatically cleared when the interrupt is
processed.
INTERRUPT ENABLE REGISTER (IE) SFR ADDRESS 0A8h
Bit Addressable
Reset State 00h
BIT 7
EA
BIT 6
EX2
BIT 5
ET2
BIT 4
ES
BIT 3
ET1
BIT 2
EX1
BIT 1
ET0
BIT 0
EX0
NOTE: Bit 6 differs from the 8032. This is a reserved bit in the 8032 and is used as a mask bit for external
interrupt 2 in the core implementation. When bit 6 is set to a 0, external interrupt 2 is disabled.
The mask bit for the HDLC interrupt source is bit 0 of the HDLC Control Register.
INTERRUPT PRIORITY REGISTER (IP) SFR ADDRESS 0B8h
Bit Addressable
Reset State 00h
BIT 7
PHDLC
BIT 6
PX2
BIT 5
PT2
BIT 4
PS
BIT 3
PT1
BIT 2
PX1
BIT 1
PT0
BIT 0
PX0
NOTE: Bit 6 and bit 7 differ from the 8032. These are reserved bits in the 8032 and are used to determine
the priority of external interrupt 2 and the HDLC in the core implementation. When bit 6 is set to a 1,
the interrupt is set to the higher priority level.
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