HCS04D View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

HCS04D

Radiation Hardened Hex Inverter

Intersil 

HCS04MS

August 1995

Radiation Hardened

Hex Inverter

Features

Pinouts

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K RAD (Si)

• SEP Effective LET No Upsets: >100 MEV-cm2/mg

• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day

(Typ)

• Dose Rate Survivability: >1 x 1012 RAD (Si)/s

• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse

• Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Gate Day

(Typ)

• Latch-Up Free Under Any Conditions

• Military Temperature Range: -55oC to +125oC

14 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T14

TOP VIEW

A1 1

Y1 2

A2 3

Y2 4

A3 5

Y3 6

14 VCC

13 A6

12 Y6

11 A5

10 Y5

9 A4

• Significant Power Reduction Compared to LSTTL ICs

GND 7

8 Y4

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 30% of VCC Max

- VIH = 70% of VCC Min

• Input Current Levels Ii ≤ 5µA at VOL, VOH

14 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835 CDFP3-F14

TOP VIEW

Description

A1

1

14

VCC

Y1

2

13

A6

The Intersil HCS04MS is a Radiation Hardened Hex Inverter. A

A2

3

12

Y6

logic level on any input forces the output to the opposite logic

Y2

4

11

A5

state.

A3

5

10

Y5

The HCS04MS utilizes advanced CMOS/SOS technology to

Y3

6

9

A4

achieve high-speed operation. This device is a member of GND

7

8

Y4

radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCS04MS is supplied in a 14 lead Ceramic flatpack (K suffix)

or a SBDIP Package (D suffix).

TRUTH TABLE

INPUTS

OUTPUTS

Ordering Information

PART

NUMBER

TEMPERATURE SCREENING

RANGE

LEVEL

PACKAGE

HCS04DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP

S Equivalent

HCS04KMSR -55oC to +125oC Intersil Class 14 Lead Ceramic

S Equivalent Flatpack

HCS04D/

Sample

+25oC

Sample

14 Lead SBDIP

HCS04K/

Sample

+25oC

Sample

14 Lead Ceramic

Flatpack

HCS04HMSR

+25oC

Die

Die

An

Yn

L

H

H

L

NOTE: L = Logic Level Low,

H = Logic level High

Functional Diagram

An

(1, 3, 5, 9, 11, 13)

Yn

(2, 4, 6, 8, 10, 12)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

25

Spec Number 518745

File Number 3046.1

Share Link: