Standard Products
UT54LVDS032LVT Low Voltage Quad Receiver with Integrated
Termination Resistor
Preliminary Data Sheet
February 14, 2003
FEATURES
INTRODUCTION
q >400.0 Mbps (200 MHz) switching rates
q +340mV differential signaling
The UT54LVDS032LV Quad Receiver is a quad CMOS
differential line receiver designed for applications requiring
ultra low power dissipation and high data rates. The device is
q 3.3 V power supply
q TTL compatible outputs
q Cold spare all pins
q Nominal 105Ω Integrated Termination Resistor
q 3.3ns maximum propagation delay
q 0.35ns maximum differential skew
q Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
designed to support data rates in excess of 400.0 Mbps (200
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The UT54LVDS032LV accepts low voltage (340mV)
differential input signals and translates them to 5V TTL o utput
levels. The receiver supports a three-state function that may be
used to multiplex outputs. The receiver also supports OPEN,
shorted and terminated (100 Ω) input fail-safe. Receiver output
will be HIGH for all fail-safe conditions.
q
q
q
q
- Total-dose: 300 krad(Si) and 1Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
Packaging options:
T - 16-lead flatpack (dual in-line)
N Standard Microcircuit Drawing TBD
- QML Q and V compliant part
E Compatible with IEEE 1596.3SCI LVDS
Compatible with ANSI/TIA/EIA 644-1996 LVDS
Standard
PM RIN1+
O RIN1-
EL RIN2+
RIN2-
EVRIN3+
D RIN3-
The UT54LVDS032LV and companion quad line driver
UT54LVDS031LV provides new alternatives to high power
pseudo-ECL devices for high speed point-to-point interface
applications.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
An integrated termination resistor will reduce component count
and save board space.
+
R1
-
+
R2
-
+
R3
-
ROUT1
ROUT2
ROUT3
IN
RIN4+
RIN4-
+
R4
-
ROUT4
EN
EN
Figure 1. UT54LVDS032LV Quad Receiver Block Diagram
1