Interrupts
7.6.2 External interrupt control register (EICR)
EICR
7
6
5
4
3
IS11
IS10
IPB
IS21
IS20
R/W
R/W
R/W
R/W
R/W
ST72324xx-Auto
Reset value: 0000 0000 (00h)
2
1
0
IPA
Reserved
R/W
-
Table 19. EICR register description
Bit Name
Function
ei2 and ei3 sensitivity
roduct(s) 7:6 IS1[1:0]
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:
- ei2 for port B[3:0] (see Table 20)
- ei3 for port B4 (see Table 21)
Bits 7 and 6 can only be written when I1 and I0 of the CC register are both set to 1
(level 3).
P Interrupt Polarity (for port B)
bsolete 5 IPB
This bit is used to invert the sensitivity of port B [3:0] external interrupts. It can be
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion
1: Sensitivity inversion
O ei0 and ei1 sensitivity
ct(s) - 4:3 IS2[1:0]
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:
- ei0 for port A[3:0] (see Table 22)
- ei1 for port F[2:0] (see Table 23)
uBits 4 and 3 can only be written when I1 and I0 of the CC register are both set to 1
rod(level 3).
P Interrupt Polarity (for port A)
This bit is used to invert the sensitivity of port A [3:0] external interrupts. It can be
lete2 IPA
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
o 0: No sensitivity inversion.
s 1: Sensitivity inversion.
Ob 1:0 - Reserved, must always be kept cleared
Table 20.
IS11
0
0
1
1
Interrupt sensitivity - ei2
IS10
External interrupt sensitivity
IPB bit = 0
IPB bit = 1
0
Falling edge and low level
Rising edge and high level
1
Rising edge only
Falling edge only
0
Falling edge only
Rising edge only
1
Rising and falling edge
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