ST72324J2-AUTO View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72324J2-AUTO

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

Supply, reset and clock management

ST72324xx-Auto

Figure 12. Reset block diagram

VDD

RESET

RON

Filter

Internal

reset

Pulse

generator

Watchdog reset

LVD reset

ct(s) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In

u a noisy environment, it is recommended to follow the guidelines mentioned in the Electrical

d characteristics section.

Pro External power-on reset

te If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must

le ensure by means of an external reset circuit that the reset signal is held low until VDD is over

o the minimum level specified for the selected fOSC frequency.

bs A proper reset signal for a slow rising VDD supply can generally be provided by an external

O RC network connected to the RESET pin.

) - Internal LVD reset

t(s Two different reset sequences caused by the internal LVD circuitry can be distinguished:

c ● Power-On reset

du ● Voltage Drop reset

ro The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or

P VDD < VIT- (falling edge) as shown in Figure 13.

teThe LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

oleInternal Watchdog reset

bs The reset sequence generated by a internal Watchdog counter overflow is shown in

O Figure 13.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that

is pulled low during at least tw(RSTL)out.

36/193

Doc ID 13841 Rev 1

Share Link: