ST72324J2-AUTO View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72324J2-AUTO

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

Central processing unit (CPU)

ST72324xx-Auto

5.3.1

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results

of the arithmetic and logic calculations as well as data manipulations.

5.3.2

Index registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas

for data manipulation (the Cross-Assembler generates a precede instruction (PRE) to

indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

5.3.3

Obsolete Product(s) - Obsolete Product(s) 5.3.4

Program counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be

executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is

the LSB) and PCH (Program Counter High which is the MSB).

Condition Code register (CC)

The 8-bit Condition Code register contains the interrupt masks and four flags representative

of the result of the instruction just executed. This register can also be handled by the PUSH

and POP instructions. These bits can be individually tested and/or controlled by specific

instructions.

CC

Reset value: 111x1xxx

7

6

5

4

3

2

1

0

1

1

I1

H

I0

N

Z

C

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Table 6. Arithmetic management bits

BIt Name

Function

Half carry

4H

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU

during an ADD or ADC instructions. It is reset by hardware during the same

instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD

arithmetic subroutines.

Negative

2N

This bit is set and cleared by hardware. It is representative of the result sign of the last

arithmetic, logical or data manipulation. It is a copy of the result 7th bit.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative (that is, the most significant bit is a logic

1).

This bit is accessed by the JRMI and JRPL instructions.

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Doc ID 13841 Rev 1

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