OR [R1R0],A
Machine code
Description
Operation
OUT PA,A
Machine code
Description
Operation
READ MR0A
Machine code
Description
Operation
READ R4A
Machine code
Description
Operation
HTG12G0
Logically OR data memory with accumulator
00011111
Data in the data memory addressed by the register pair “R1,R0” is logical OR
with the accumulator.
M(R1,R0) ← M(R1,R0) “OR” ACC
Output accumulator data to port A
00110000
The data in the accumulator is transferred to port PA and latched.
PA ← ACC
Read ROM code of current page to M(R1,R0) and ACC
01001110
The 8-bit ROM code (current page) addressed by ACC and R4 is moved to the
data memory M(R1,R0) and the accumulator. The high nibble of the ROM
code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to
the accumulator. The address of the ROM code is specified below:
Current page → ROM code address bit 11~8
ACC → ROM code address bit 7~4
R4 → ROM code address bit 3~0
M(R1,R0) ← ROM code (high nibble)
ACC ← ROM code (low nibble)
Read ROM code of current page to R4 and accumulator
01001100
The 8-bit ROM code (current page) addressed by ACC and M(R1,R0) is moved
to the working register R4 and the accumulator. The high nibble of the ROM
code is loaded to R4 and the low nibble of the ROM code is loaded to the
accumulator. The address of the ROM code is specified below:
Current page → ROM code address bit 11~8
ACC → ROM code address bit 7~4
M(R1,R0) → ROM code address bit 3~0
R4 ← ROM code (high nibble)
ACC ← ROM code (low nibble)
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14th May ’99