AD7872TQ View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7872TQ Datasheet PDF : 24 Pages
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AD7871/AD7872
Data Sheet
Pin No.
26
27
28
Mnemonic
VIN
VSS
14/8/CLK
Description
Analog Input. The input range is ±3 V.
Negative Supply, –5 V ± 5%.
Three-Function Input. Defines both the parallel and serial data formats. With this pin at +5 V, the output data is
14-bit parallel only. With this pin at 0 V, both byte and serial data are available, and the SCLK is noncontinuous.
With this pin at –5 V, both byte and serial data are available and the SCLK is continuous.
Table 5. Byte Output Format
HBEN
DB7
DB6
HIGH
LOW
LOW
LOW
DB7
DB6
DB5
DB13
DB5
DB4
DB12
DB4
DB3
DB11
DB3
DB2
DB10
DB2
DB1
DB0
DB9
DB8
DB1
DB0
CONTROL 1
CONVST 2
CLK 3
SSTRB 4
SCLK 5
SDATA 6
NC 7
DGND 8
AD7872
TOP VIEW
(Not to Scale)
16 VDD
15 VSS
14 VIN
13 REFOUT
12 AGND
11 CREF
10 NC
9 VDD
NOTES
1. NC = NO CONNECT.
Figure 7. AD7872 DIP, SOIC
Table 6. AD7872 Pin Function Descriptions
Pin No. Mnemonic Description
1
CONTROL
Control Input. With this pin at 0 V, the SCLK is noncontinuous; with this pin at −5 V, the SCLK is continuous.
2
CONVST
Convert Start. A low to high transition on this input puts the track/hold into the hold mode. This input is
asynchronous to the CLK.
3
CLK
Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to VSS
enables the internal laser-trimmed oscillator.
4
SSTRB
Serial Strobe. This is an active low three-state output that provides a framing pulse for serial data. An external
4.7 kΩ pull-up resistor is required on SSTRB.
5
SCLK
Serial Clock. SCLK is the gated serial clock output derived from the internal or external ADC clock. If the 14/8/
CLK input is at −5 V, then the SCLK runs continuously. With CONTROL at 0 V, it is gated off (three-state) after the
serial transmission is complete. SCLK is an open-drain output and requires an external 2 kΩ pull-up resistor.
6
SDATA
Serial Data. This is the three-state serial data output used in conjunction with SCLK and SSTRB in a serial data
transmission. Serial data is valid on the falling edge of SCLK, when SSTRB is low. An external 4.7 kΩ pull-up
resistor is required on SDATA.
7
NC
No Connect.
8
DGND
Digital Ground. Ground return for digital circuitry.
9
VDD
Positive Supply for Analog Circuitry, +5 V ± 5%.
10
NC
No Connect.
11
CREF
Decoupling Point for On-Chip Reference. Connect a 10 nF capacitor between this pin and AGND.
12
AGND
Analog Ground. Ground reference for analog circuitry.
13
REFOUT
Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is
500 µA.
14
VIN
Analog Input. The input range is ±3 V.
15
VSS
Negative Supply, −5 V ± 5%.
16
VDD
Positive Supply for Analog Circuitry, +5 V ± 5%. Connect Pin 16 and Pin 9 together.
Rev. E | Page 8 of 24
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