AD7871/AD7872
Data Sheet
MODE 1 INTERFACE
A conversion is initiated by a low going pulse on the CONVST
input. The rising edge of this CONVST pulse starts the
conversion and drives the track-and-hold amplifier into its hold
mode. The BUSY/INT status output assumes its INT function
in this mode. INT is normally high and goes low at the end of
conversion. This INT line can be used to interrupt the
microprocessor. A read operation to the AD7871 accesses the
data and the INT line is reset high on the falling edge of CS and
RD. The CONVST input must be high when CS and RD are
brought low for the AD7871 to operate correctly in this mode.
It is important, especially in systems where the conversion start
(CONVST) pulse is asynchronous to the microprocessor, to
ensure that a parallel or byte data read is not attempted during a
conversion. Trying to read data during a conversion can cause
errors to the conversion in progress. Avoid pulsing the
CONVST line a second time before the conversion ends
because it can cause errors in the conversion result. In
applications where precise sampling is not critical, the
CONVST pulse can be generated from the microprocessor WR
line OR-gated with the AD7871 CS input. In some applications,
depending on power supply turn-on time, the AD7871/AD7872
may perform a conversion on power-up. In this case, the INT
line on the AD7871 will power up low, and a dummy read to
the device will be required to reset the INT line before starting
conversion.
Figure 14 shows the Mode 1 timing diagram for a 14-bit parallel
data output format (14/8/CLK = 5 V). A read to the AD7871 at
the end of conversion accesses all 14 bits of data at the same
time. Serial data is not available for this data output format.
t1
CONVST
TRACK-AND-HOLD
GOES INTO HOLD
CS
t2
t4
t3
RD
INT
DATA
TRACK-AND-HOLD RETURNS
TO TRACK AND
ACQUISITION BEGINS
t5
tCONVERT
THREE-STATE
t7
t6
VALID
DATA
DB13 TO DB0
Figure 14. Mode 1 Timing Diagram, 14-Bit Parallel
The Mode 1 function timing diagram for byte and serial data is
shown in Figure 15. INT goes low at the end of conversion and
is reset high by the first falling edge of CS and RD. This first
read at the end of the conversion can either access the low byte
or high byte of data depending on the status of HBEN
(Figure 15 shows low byte for example only). The diagram
shows both the SCLK output going into three-state at the end of
transmission and a continuously running clock (dashed line).
CONVST
t1
TRACK-AND-HOLD GOES INTO HOLD
HBEN1
CS
RD
INT
DATA
DON’T CARE
TRACK-AND-HOLD RETURNS TO TRACK.
SIGNAL ACQUISITION BEGINS
tCONVERT
THREE-STATE
t8
t9
t2
t5
t4
t3
t7
t6
VALID
DATA
DB7 TO DB0
SSTRB2
t10
t11
t13
SCLK3
SDATA
LEADING
ZEROS
t12
DB13 DB12 DB11 DB10
t14
DB0
SERIAL DATA
1TIMES t2, t3, t4, t8, AND t9 ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
2EXTERNAL 4.7kΩ PULL-UP RESISTOR.
3EXTERNAL 2kΩ PULL-UP RESISTOR. CONTINUOUS SCLK (DASHED LINE) WHEN 14/8/CLK
(CONTROL) = –5V; NONCONTINUOUS WHEN 14/8/CLK (CONTROL) = 0V.
Figure 15. Mode 1 Timing Diagram, Byte or Serial Read
VALID
DATA
DB11 TO DB8
Rev. E | Page 12 of 24