256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Functional Block Diagrams
Functional Block Diagrams
Figure 2: 8 Meg x 32
A0–A18, B0, B1, B2
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh
Counter
Row Decoder
Memory Array
Bank 0
Row Decoder
Memory Array
Bank 1
Row Decoder
Memory Array
Bank 2
Row Decoder
Memory Array
Bank 3
Row Decoder
Memory Array
Bank 4
Row Decoder
Memory Array
Bank 5
Row Decoder
Memory Array
Bank 6
Row Decoder
Memory Array
Bank 7
Data Valid
Data Read Strobe
Input Buffers Output Buffers Control Logic and Timing Generator
DVLD
DQS[3:0], DQS#[3:0]
DQ0–DQ31
Note: When the BL = 4 setting is used, A18 is a “Don’t Care.“
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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