256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
IEEE 1149.1 Serial Boundary Scan (JTAG)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The RLDRAM incorporates a serial boundary scan Test Access Port (TAP). This port
operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions from the IEEE specifica-
tion are excluded because their inclusion places an added delay in the critical speed
path of the RLDRAM. Note that the TAP controller functions in a manner that does not
conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 1.8V I/O logic levels.
The RLDRAM contains a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling The JTAG Feature
It is possible to operate the RLDRAM without using the JTAG feature. To disable the TAP
controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS
are internally pulled up and may be unconnected. They may alternately be connected to
VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the
device will come up in a reset state which will not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising
edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the
rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used.
The ball is pulled up internally, resulting in a logic HIGH level.
Test Data-in (TDI)
The TDI ball is used to serially input information into the registers and can be connected
to the input of any of the registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For information on loading
the instruction register, see Figure 27 on page 28. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Figure 28 on page 29.)
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.