256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Read Basic Information
Read Basic Information
Read accesses are initiated with a READ command, as shown in Figure 17. Row and
bank addresses are provided with the READ command.
During READ bursts, the memory device drives the read data edge-aligned with the DQS
signal. After a programmable READ latency, data is available at the outputs. The data
valid signal indicates that valid data will be present in the next half clock cycle.
The skew between DQS and the crossing point of CK is specified as tCKDQS. tDQSQ is
the skew between DQS and the last valid data edge considered over all the data gener-
ated at the DQ signals. tDQSQ is derived at each DQS clock edge and is not cumulative
over time.
After completion of a burst, assuming no other commands have been initiated, output
data (DQ) will go to High-Z. Back-to-back READ commands are possible, producing a
continuous flow of output data.
The data valid window is derived from each DQS transition and is defined as:
MIN (tCKH, tCKL) - 2 tDQSQ(MAX)
Any READ burst may be followed by a subsequent WRITE command. Figures 21–24 on
page 24–25 illustrate the timing requirements for a READ followed by a WRITE. Depend-
ing on the programmed READ latency, a READ-to-WRITE delay occurs in order to pre-
vent bus contention. Some systems having long line lengths or severe skews may need
additional idle cycles inserted.
Figure 17: READ Command
CK#
CK
CS#
AS#
WE#
REF#
A(20:0)
A
BA(2:0)
BA
Note:
DON’T CARE
A: address
BA: bank address.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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©2001 Micron Technology, Inc. All rights reserved.