256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Write Basic Information
Figure 15: Write Data Mask Timing: BL = 4; WL = 1
0
1
2
3
4
5
6
7
8
CK#
CK
CMD
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
ADDR
A
BA0
A
BA2
A
BA4
A
BA6
A
BA0
WL = 1
DM0
DM1
DQ
D0a D0b D0c D0d D2a D2b D2c D2d D4a D4b D4c D4d D6a D6b D6c D6
Figure 16: WRITE followed by READ: BL = 4; RL = 5; WL = 1
Data
masked
0
1
2
3
4
5
6
7
8
9
CK#
CK
CMD
WR
RD
WR
RD
NOP
NOP
NOP
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
WL = 1
A
A
BA3
BA2
RL = 5
DQ
D0a D0b D0c D0d D3a D3b D3c D3d
Q1a Q1b Q1c Q1d Q2a Q1d Q2a
DQSx
DQSx#
Note:
A/BAx: address A of bank x
WR: WRITE
Dxy: data y to bank x
WL: WRITE latency
RD: READ
Qxy: data y from bank x
RL: READ latency.
DON’T CARE
UNDEFINED
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
20
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©2001 Micron Technology, Inc. All rights reserved.