256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Write Basic Information
Table 11: Timing Parameters
Symbol
tDS
tDH
-33
Min/Max
0.5
0.5
-4
Min/Max
0.5
0.5
Figure 12: WRITE Burst Basic Sequence: BL = 2; WL = 3
0
1
2
3
4
5
CK#
CK
-5
Min/Max
0.5
0.5
6
7
CMD
WR
WR
WR
WR
WR
WR
WR
WR
Units
ns
ns
8
WR
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA6
A
BA7
A
BA0
WL = 3
DQ
D0a D0b D1a D1b D2a D2b D3a D3b D4a D4b D5a D5
DON’T CARE
Figure 13: WRITE Burst Basic Sequence: BL = 4; WL = 2
0
1
2
3
4
5
6
7
8
CK#
CK
CMD
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
WL = 2
DQ
D0a D0b D0c D0d D1a D1b D1c D1d D2a D2b D2c D2d D3a D3
DON’T CARE
Notes: 1. A/BAx: address A of bank x
WR: WRITE
Dxy: data y to bank x
WL: WRITE latency.
2. Any free bank may be used in any given CMD. The sequence shown is only one example of
a bank sequence.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.