MT49H16M16 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT49H16M16

REDUCED LATENCY DRAM (RLDRAM®)

Micron Technology 

256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM

Write Basic Information

Write Basic Information

Write accesses are initiated with a WRITE command, as shown in the Figure 10. Row and

bank addresses are provided together with the WRITE command.

During WRITE commands, data will be registered at both edges of CK according to the

programmed burst length (BL). The first valid data will be registered with the first rising

CK edge WL cycles after the WRITE command has been issued.

Any WRITE burst may be followed by a subsequent READ command. Figure 16 on

page 20 illustrates the timing requirements for a WRITE followed by a READ for burst of

four.

Setup and hold times for incoming DQ relative to the CK edges are specified as tDS and

tDH.

The first or second part of the incoming data burst is masked if the corresponding DMx

signal is sampled HIGH along with the WRITE command. The setup and hold times for

data mask are the same as for address and command.

Figure 10: WRITE Command

CS#

AS#

WE#

REF#

DM(1:0)

DM

A(20:0)

A

BA(2:0)

BA

Note:

DON’T CARE

A: address

BA: bank address

DM: data mask.

Figure 11: Basic WRITE Burst Timing

CK#

CK

Write

Latency

DQ

tDS tDH

D0

D1

tDS tDH

D2

D3

DON’T CARE

pdf: 09005aef81121545/source: 09005aef810c0ffc

256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN

17

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001 Micron Technology, Inc. All rights reserved.

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