SP207H View Datasheet(PDF) - Signal Processing Technologies

Part Name

Description

Manufacturer

SP207H

+5V High–Speed RS-232 Transceivers

Signal Processing Technologies 

VCC = +5V

+

C1 –

–5V

+5V

+

C2 –

–5V

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

Figure 1. Charge Pump — Phase 1

negative side of capcitor C2. There is a free–

running oscillator that controls the four phases

of the voltage shifting. A description of each

phase follows.

Phase 1

— VSS charge storage —During this phase of the

clock cycle, the positive side of capacitors C1

and C2 are initially charged to +5V. Cl+ is then

switched to ground and the charge in C1– is

transferred to C2–. Since C2+ is connected to

+5V, the voltage potential across capacitor C2 is

now 10V.

Phase 2

— V transfer — Phase two of the clock con-

SS

nects the negative terminal of C2 to the VSS

storage capacitor and the positive terminal of C2

to ground, and transfers the generated –l0V to

C . Simultaneously, the positive side of capaci-

3

tor C 1 is switched to +5V and the negative side

is connected to ground.

Phase 3

— VDD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C produces –5V in the negative

1

terminal of C1, which is applied to the negative

side of capacitor C2. Since C2+ is at +5V, the

VCC = +5V

voltage potential across C2 is l0V.

Phase 4

— VDD transfer — The fourth phase of the clock

connects the negative terminal of C2 to ground,

and transfers the generated l0V across C2 to C4,

the VDD storage capacitor. Again, simultaneously

with this, the positive side of capacitor C1 is

switched to +5V and the negative side is con-

nected to ground, and the cycle begins again.

Since both V+ and V– are separately generated

from V ; in a no–load condition V+ and V– will

CC

be symmetrical. Older charge pump approaches

that generate V– from V+ will show a decrease in

the magnitude of V– compared to V+ due to the

inherent inefficiencies in the design.

The clock rate for the charge pump typically

operates at 15kHz. The external capacitors can

be as low as 0.1µF with a 16V breakdown

voltage rating.

Transmitter/Driver

The drivers are inverting transmitters which have

been improved for speed over the SP200 Series.

The transmitters accept either TTL or CMOS

inputs and output the RS-232 signals at data rates

over 400kbps. Typically, the RS-232 output volt

+

C1 –

+

C2 –

–10V

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

Figure 2. Charge Pump — Phase 2

TGoddard/SP207H/9614R0

SP207H/SP211H High–Speed Transceivers

5

© Copyright 2000 Sipex Corporation

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