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PIC18F2450 View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC18F2450 Datasheet PDF : 324 Pages
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PIC18F2450/4450
FIGURE 1-2:
PIC18F4450 (40/44-PIN) BLOCK DIAGRAM
Table Pointer<21>
Data Bus<8>
inc/dec logic
21
20
88
PCLATU PCLATH
PCU PCH PCL
Program Counter
Address Latch
Program Memory
(24/32 Kbytes)
Data Latch
31 Level Stack
STKPTR
Data Latch
Data Memory
(2 Kbytes)
Address Latch
12
Data Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Access
Bank
12
8
Table Latch
inc/dec
logic
ROM Latch
Instruction Bus <16>
IR
Address
Decode
PORTA
PORTB
PORTC
VDD, VSS
OSC1(2)
OSC2(2)
T1OSI
T1OSO
ICPGC(3)
ICPGD(3)
ICPORTS(3)
ICRST(3)
MCLR(1)
VUSB
Instruction
Decode &
Control
State Machine
Control Signals
8
PRODH PRODL
Internal
Oscillator
Block
INTRC
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
USB Voltage
Regulator
3
BITOP
8
8 x 8 Multiply
8
W
8
8
8
8
ALU<8>
8
Band Gap
Reference
PORTD
PORTE
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI/RCV
RA5/AN4/HLVDIN
OSC2/CLKO/RA6
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2/VMO
RB3/AN9/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE0/AN5
RE1/AN6
RE2/AN7
MCLR/VPP/RE3(1)
BOR
HLVD
Timer0
Timer1
Timer2
CCP1
EUSART
ADC
10-Bit
USB
Note 1:
2:
3:
RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 18.9 “Special ICPORT Features (Designated
Packages Only)” for additional information.
© 2008 Microchip Technology Inc.
DS39760D-page 11
 

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