A(18:0)
tAVET
En
tAVAV3
tETEF
tEFAX
or
tAVET
En
tETEF
tEFAX
Wn
tWLEF
Dn(7:0)
Qn(7:0)
tWLQZ
APPLIED DATA
tDVEF
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle.
2. Either En scenario above can occur.
3. G high for tAVAV cycle.
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
300 ohms
VLOAD = 1.55V
CMOS
VDD-0.05V
10%
0.5V
50pF
< 5ns
Notes:
1. 50pF including scope probe and test socket capacitance.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = VDD/2).
Input Pulses
Figure 6. AC Test Loads and Input Waveforms
90%
10%
< 5ns
10