5962G9475401QLX View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
5962G9475401QLX Datasheet PDF : 19 Pages
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C2
C1
C0
0
0
0
0
0
1
X
1
0
X
1
1
1
0
0
1
0
1
Notes:
1. 0 equals programmed low or programmed.
2. 1 equals programmed high or unprogrammed.
3. X equals don’t care.
Table 1. Macrocell Configuration Table1, 2, 3
Output Type
Polarity
Registered
Registered
Combinatorial
Combinatorial
Registered
Registered
Active LOW
Active HIGH
Active LOW
Active HIGH
Active LOW
Active HIGH
Feedback
Registered
Registered
I/O
I/O
I/O
I/O
OVERVIEW
The UT22VP10 RADPAL architecture (see figure 1) has 12 ded-
icated inputs and 10 I/Os to provide up to 22 inputs and 10
outputs for creating logic functions. At the core of the device
is a one-time programmable anti-fuse AND array that drives a
fixed OR array. With this structure, the UT22VP10 can imple-
ment up to 10 sum-of-products logic expressions.
Associated with each of the 10 OR functions is a macrocell
which is independently programmed to one of six different con-
figurations. The one-time programmable macro cells allow
each I/O to create sequential or combinatorial logic functions
with either Active-High or Active-Low polarity.
LOGIC ARRAY
The one-time programmable AND array of the UT22VP10
RADPAL is formed by input lines intersecting product terms.
The input lines and product terms are used as follows:
44 input lines:
• 24 input lines carry the true and complement of the signals
applied to the input pins
• 20 lines carry the true and complement values of feedback
or input signals from the 10 I/Os
132 product terms:
• 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and
16) used to form logic sums
• 10 output enable terms (one for each I/O)
• 1 global synchronous preset term
• 1 global asynchronous reset term
At each input-line/product-term intersection there is an anti-
fuse cell which determines whether or not there is a logical
connection at that intersection. A product term which is con-
nected to both the true and complement of an input signal will
always be logical zero, and thus will not effect the OR function
that it drives. When there are no connections on a product term
a Don’t Care state exists and that term will always be a logical
one.
PRODUCT TERMS
The UT22VP10 provides 120 product terms that drive the 10
OR functions. The 120 product terms connect to the outputs in
two groups of 8, 10, 12, 14, and 16 to form logical sums.
MACROCELL ARCHITECTURE
The output macrocell provides complete control over the archi-
tecture of each output. Configuring each output independently
permits users to tailor the configuration of the UT22VP10 to
meet design requirements.
Each I/O macrocell (see figure 2) consists of a D flip-flop and
two signal-select multiplexers. Three configuration select bits
controlling the multiplexers determine the configuration of
each UT22VP10 macrocell (see table 1). The configuration se-
lect bits determine output polarity, output type (registered or
combinatorial) and input feedback type (registered or I/O). See
figure 3 for equivalent circuits for the macrocell configurations.
OUTPUT FUNCTIONS
The signal from the OR array may be fed directly to the output
pin (combinatorial function) or latched in the D flip-flop (reg-
istered function). The D flip-flop latches data on the rising edge
of the clock. When the synchronous preset term is satisfied, the
Q output of the D flip-flop output will be set logical one at the
next rising edge of the clock input. Satisfying the asynchronous
clear term sets Q logical zero, regardless of the clock state. If
both terms are satisfied simultaneously, the clear will override
the preset.
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