5962F9475401VYC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962F9475401VYC

Universal RADPAL™

Aeroflex UTMC 

POWER-UP RESET

The power-up reset feature ensures that all flip-flops will be

reset to LOW after the device has been powered up. The output

state will depend on the programmed pattern. This feature is

valuable in simplifying state machine initialization. See figure

6 for a timing diagram. Due to the synchronous operation of the

power-up reset and the wide range of ways VDD can rise to its

steady state, the following five conditions are required to ensure

a valid power-up reset.

1. The voltage supplied to the VDD pin(s) must be equal to 0V

prior to the intended power-up sequence.

2. The voltage on VDD must rise from 0V to 1V at a rate of

0.1V/s or faster.

3. The VDD rise must be continuously increasing with respect

to time, through 3V, and monotonic thereafter.

4. Following reset, the clock input must not be driven from

LOW to HIGH until all applicable input and feedback setup

times are met.

5. The power-up voltage must meet the minimum VDD require-

ments described by the following device dependent and tem-

perature dependent equations:

SMD Device types 01, 02, 03, 04, 08 CMOS and TTL

VDD =4.61V -0.0090*(oC)

SMD Device types 05, 06, 07

CMOS

VDD =4.41 -0.0090* (oC)

Note: The minimum VDD requirement above is not applicable

if the UT22VP10 application is purely combinatorial (i.e. no

registered outputs).

VDD

VDD min

VDD

REGISTERED

ACTIVE-LOW

OUTPUT

CLOCK

tPR

tS

tWL

Figure 6. Power-Up Reset Waveform

RADIATION HARDNESS

The UT22VP10 RADPAL incorporates special design and layout features which allow operation in high-level radiation environments.

UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both

the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup

immunity, UTMC builds radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process.

RADIATION HARDNESS DESIGN SPECIFICATIONS1

PARAMETER

Total Dose

LET Threshold

CONDITION

+25°C per MIL-STD-883 Method 1019

-55°C to +125°C

Neutron Fluence

1MeV equivalent

MINIMUM

1.0E6

50

1.0E14

UNIT

rads(Si)

MeV-cm2/mg

n/cm2

Note:

1. The RADPAL will not latchup during radiation exposure under recommended operating conditions.

12

Share Link: