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PIC12C671T-04E/JW 데이터 시트보기 (PDF) - Microchip Technology

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PIC12C671T-04E/JW Datasheet PDF : 129 Pages
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4.5 Indirect Addressing, INDF and FSR
Registers
The INDF Register is not a physical register. Address-
ing the INDF Register will cause indirect addressing.
Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF Register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF Register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR Register and the IRP bit
(STATUS<7>), as shown in Figure 4-4. However, IRP is
not used in the PIC12C67X.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
PIC12C67X
EXAMPLE 4-1: INDIRECT ADDRESSING
movlw
movwf
NEXT
clrf
incf
btfss
goto
CONTINUE
:
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
FIGURE 4-4: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1 RP0(1) 6
from opcode
0
Indirect Addressing
IRP(1) 7
FSR register
0
bank select location select
00
01
00h
bank select
10
11
180h
location select
Data
Memory
not used
7Fh
Bank 0
Bank 1 Bank 2
1FFh
Bank 3
For register file map detail see Figure 4-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
© 1999 Microchip Technology Inc.
DS30561B-page 23

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