OPTION (w) : Chip option configuration (All are "0" in Chip Reset).
PWMF = 1 → Selects 94KHz PWM frequency.
= 0 → Selects 47KHz PWM frequency.
DIV253 = 1 → PWM pulse width is 253-step resolution.
= 0 → PWM pulse width is 256-step resolution.
FclkE = 1 → Double CPU clock freq.
IICpass = 1 → HSCL/HSDA pin bypasses to ISCL/ISDA pin in DDC2 mode.
= 0 → Separates Master and Slave IIC block.
ENSCL = 1 → Enables slave IIC block to hold HSCL pin low while MTV212M64i is unable to
catch up the external master's speed.
Msel = 1 → Master IIC block connects to HSCL/HSDA pins.
= 0 → Master IIC block connects to ISCL/ISDA pins.
MIICF1,MIICF0 = 1,1 → Selects 400KHz Master IIC frequency.
= 1,0 → Selects 200KHz Master IIC frequency.
= 0,1 → Selects 50KHz Master IIC frequency.
= 0,0 → Selects 100KHz Master IIC frequency.
SlvAbs1,SlvAbs0 : Slave address length of Slave IIC block A.
= 1,0 → 5-bits slave address.
= 0,1 → 6-bits slave address.
= 0,0 → 7-bits slave address.
XBANK (r/w) : Auxiliary RAM bank switch.
= 0 → Selects AUXRAM bank 0.
= 1 → Selects AUXRAM bank 1.
= 2 → Selects AUXRAM bank 0.
= 3 → Selects AUXRAM bank 1.
= 4 → Selects AUXRAM bank 0.
= 5 → Selects AUXRAM bank 1.
4. Extra I/O
The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode only. Port5 can be used as
both output and input for that the pin of Port5 is open drain type, users must write corresponding bit of Port5
to "1" in input mode.
Reg name addr
PORT4 38h (w)
PORT5 39h (r/w)
PORT4 (w) : Port 4 data output value.
PORT5 (r/w) : Port 5 data input/output value.
5. PWM DAC
Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of
PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if the content of DAC register is FFH. Writing
00H to DAC register generates stable low output.