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MTV212MS64I View Datasheet(PDF) - Myson Century Inc

Part Name
Description
Manufacturer
MTV212MS64I Datasheet PDF : 26 Pages
First Prev 21 22 23 24 25 26
MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
CRCin = CRC[15]^DATAin;
CRC[15:0] = {CRC[14]^CRCin, CRC[13:2], CRC[1]^CRCin, CRC[0], CRCin};
Where
^ = XOR
example:
data_byte
F6H
28H
C3H
CRC_register_remainder
FFFFH
FF36H
34F2H
7031H
10.6 Reset Device
After the Flash has completed programming and verified OK, the ISP Host can use “Command Write”
with Reset_CPU command to wake up MTV212M64i.
Reg name addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ISPSLV 0bh (w)
ISP Slave address
ISPEN 0ch (w)
Write 93h to enable ISP Mode
Test Mode Condition
In normal application, users should avoid the MTV212M64i entering its test mode or writer mode, outlined as
follows, adding pull-up resistor to DA8 and DA9 pins is recommended.
Test Mode A: RESET=1 & DA9=1 & DA8=0 & STO=0
Test Mode B: RESET's falling edge & DA9=1 & DA8=0 & STO=1
Writer Mode: RESET=1 & DA9=0 & DA8=1
Memory Map of XFR
Reg name
IICCTR
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
MBUF
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SL VB ADR
DBUF
ISPSLV
ISPEN
ADC
ADC
WDT
DA0
DA1
addr
00h (r/w)
01h (r)
02h (r)
03h (r)
03h (w)
04h (w)
05h (r/w)
06h (r)
06h (w)
07h (w)
08h (r)
08h (w)
09h (w)
0Ah (w)
0bh (w)
0ch (w)
10h (w)
10h (r)
18h (w)
20h (r/w)
21h (r/w)
bit7
DDC2
WadrB
MAckIn
TXBI
ETXBI
ENSlvA
ENSlvB
ENADC
WEN
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MAckO P
S
WadrA SlvRWB SAckIn SLVS
SlvAlsb1 SlvAlsb0
Hifreq Hbusy
RCBI SlvBMI TXAI RCAI SlvAMI DbufI MbufI
SlvBMI
SlvAMI
MbufI
ERCBI ESlvBMI ETXAI ERCAI ESlvAMI EDbufI EMbufI
Master IIC receives/transmits data buffer
Slave A IIC receives buffer
Slave A IIC transmits buffer
Slave A IIC address
Slave B IIC receives buffer
Slave B IIC transmits buffer
Slave B IIC address
DDC1 transmits data buffer
ISP Slave address
Write 93h to enable ISP Mode
SADC3 SADC2 SADC1 SADC0
ADC convert result
WCLR
WDT2 WDT1 WDT0
Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Revision 0.9
- 21 -
2000/11/17
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