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MTV212MS64I View Datasheet(PDF) - Myson Century Inc

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MTV212MS64I Datasheet PDF : 26 Pages
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(Rev 0.9)
, where
S = start or re-start
P = stop
K = ack by host (0 or 1)
k = ack by slave
tttttt = ISP slave address
cccccccc = command
x = don’t care
X = not defined
AAAAAAAA = Flash_address[15:8]
aaaaaaaa = Flash_address[7:0]
RRRRRRRR = CRC_register[15:8]
rrrrrrrr = CRC_register[7:0]
dddddddd = Flash_data
cccccccc = 10100xxx Program
cccccccc = 00110xxx Page Erase 128 bytes (Erase)
cccccccc = 01101xxx Erase entire Flash (Blank)
cccccccc = 11010xxx Clear CRC_register (Clr_CRC)
cccccccc = 01001xxx Reset MTV212M64i (Reset_CPU)
10.1 ISP Command Write
The 2nd byte of “Command Write” can define the operating mode of MTV212M64i in its “Data Write” stage,
clear CRC register, or reset MTV212M64i. The 3rd byte of Command Write defines the page address (A15-8)
of Flash memory. A Command Write may consist of 1,2 or 3 bytes.
10.2 ISP Command Read
The 2nd byte echoes the current command in ISP slave. The 3rd and 4th byte reflect the current Flash address.
The 5th and 6th byte report the CRC result. A Command Read may consist of 2,3,4,5 or 6 bytes.
10.3 ISP Data Write
The 2nd byte defines the low address (A7-0) of Flash. After receiving the 3rd byte, the MTV212M64i will
execute a Program/Erase/Blank command depending on the preceding “Command Write”. The low address
of Flash will increase every time when ISP slave acknowledges the data byte. The Blank/Erase command
needs one data byte (content is “don’t care”). The executing time is 4mS. During the 4mS period, the ISP
slave does not accept any command/data and returns non-ack to any IIC bus activity. The Program
command may have 1-256 data bytes. The program cycle time is 60us. If the ISP slave is unable to
complete the program cycle in time, it will return non-ack to the following data byte. In the meantime, the low
address does not increase and the CRC does not count the non-acked data byte. A Data Write may consist
of 1,2 or more bytes.
Data Write (Blank/Erase)
S-tttttt00k-aaaaaaaak-ddddddddk-P ... S-ttttttxxk-
|-----Min. 4mS----|
Data Write (Program)
S-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ...
|Min. 60uS|
10.4 ISP Data Read
The 1st and 2nd byte are the same as “Data Write” to define the low address of Flash. Between the 2nd and 3rd
byte, the ISP host may issue Stop-Start or only Re-Start. From the 4th byte, the ISP slave sends the data
byte of Flash to ISP Host. The low address automatically increases every time when data byte is transferred.
10.5 Cyclic Redundancy Check (CRC)
To shorten the verify time, the ISP slave providse a simple way to check whether data error occurs during
the program data transfer. After the ISP Host sends a lot of data bytes to ISP slave, Host can use Command
Read to check result of CRC register instead of reading every byte in Flash. The CRC register counts every
data byte which ISP slave acknowledges during “Data Write” period. However, the low address byte and the
data byte of Erase/Blank are not counted. The Clear CRC command will write all “1” to the 16-bit CRC
register. For CRC generation, the 16-bit CRC register is seeded with all “1” pattern (by device reset or Clear
CRC command). The data byte shifted into the CRC register is Msb first. The real implementation is
described as follows:
Revision 0.9
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