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MTV212MS64I View Datasheet(PDF) - Myson Century Inc

Part Name
Description
Manufacturer
MTV212MS64I Datasheet PDF : 26 Pages
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MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
EDbufI = 1
EMbufI = 1
Enables DDC1 data buffer interrupt.
Enables Master IIC bus interrupt.
Mbuf (w) :
Master IIC data shift register, after START and before STOP condition, writing this register
will resume transmission of MTV212M64i to the IIC bus.
Mbuf (r) :
Master IIC data shift register, after START and before STOP condition, reading this register
will resume receiving of MTV212M64i from the IIC bus.
RCABUF (r) : Slave IIC block A receives data buffer.
TXABUF (w) : Slave IIC block A transmits data buffer.
SLVAADR (w) : Slave IIC block A's enable and address.
ENslvA = 1 Enables slave IIC block A.
= 0 Disables slave IIC block A.
bit6-0 :
Slave IIC address A to which the slave block should respond.
RCBBUF (r) : Slave IIC block B receives data buffer.
TXBBUF (w) : Slave IIC block B transmits data buffer.
SLVBADR (w) : Slave IIC block B's enable and address.
ENslvB = 1 Enables slave IIC block B.
= 0 Disables slave IIC block B.
bit6-0 :
Slave IIC address B to which the slave block should respond.
8. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of power supply is below 4.0V(+/-0.2V) for a specific period of time, the LVR will
generate a chip reset signal. After the power supply is above 4.0V(+/-0.2V), LVR maintains in reset state for
144 Xtal cycle to guarantee the chip exit reset condition with a stable X'tal oscillation.
The WatchDog Timer automatically generates a device reset when it is overflowed. The interval of overflow
is 0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer
function is disabled after power on reset, users can activate this function by setting WEN, and clear the timer
by set WCLR.
9. A/D converter
The MTV212M64i is equipped with three 6-bit A/D converters, S/W can select the current convert channel by
setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./12288. The ADC compare the input
pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output value is N when pin voltage
is greater than VDD*N/64 and smaller than VDD*(N+1)/64.
Reg name addr
bit7
bit6
bit5
ADC
10h (w) ENADC
ADC
10h (r)
WDT
18h (w) WEN WCLR
bit4
bit3
bit2
bit1
bit0
SADC3 SADC2 SADC1 SADC0
ADC convert Result
WDT2 WDT1 WDT0
WDT (w) :
WatchDog Timer control register.
WEN
= 1 Enables WatchDog Timer.
WCLR
= 1 Clears WatchDog Timer.
WDT2: WDT0 = 0 Overflow interval = 8 x 0.25 sec.
Revision 0.9
- 18 -
2000/11/17
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