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MTV212MS64I View Datasheet(PDF) - Myson Century Inc

Part Name
Description
Manufacturer
MTV212MS64I Datasheet PDF : 26 Pages
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MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
IICCTR (r/w) : IIC interface control register.
DDC2 = 1 MTV212M64i is in DDC2 mode, write "0" can clear it.
= 0 MTV212M64i is in DDC1 mode.
MAckO = 1 In master receive mode, NACK is returned by MTV212M64i.
= 0 In master receive mode, ACK is returned by MTV212M64i.
S, P = , 0 Start condition when Master IIC is not during transfer.
= X, ↑ → Stop condition when Master IIC is not during transfer.
= 1, X Will resume transfer after a read/write MBUF operation.
= X, 0 Force HSCL low and occupy the master IIC bus.
* A write/read MBUF operation can be recognized only after 10us of the MbufI flag's rising edge.
IICSTUS (r) : IIC interface status register.
WadrB = 1 The data in RCBBUF is word address.
WadrA = 1 The data in RCABUF is word address.
SlvRWB = 1 Current transfer is slave transmit
= 0 Current transfer is slave receive
SAckIn = 1 The external IIC host respond NACK.
SLVS = 1 The slave block has detected a START, cleared when STOP detected.
SlvAlsb1,SlvAlsb0 : The 2 LSB which host sends to Slave A block.
MAckIn = 1 Master IIC bus error, no ACK received from the slave IIC device.
= 0 ACK received from the slave IIC device.
Hifreq = 1 MTV212M64i has detected a higher than 200Hz clock on the VSYNC pin.
Hbusy = 1
Host drives the HSCL pin to low.
INTFLG (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serving the interrupt routine.
SlvBMI = 1 No action.
= 0 Clears SlvBMI flag.
SlvAMI = 1 No action.
= 0 Clears SlvAMI flag.
MbufI = 1 No action.
= 0 Clears Master IIC bus interrupt flag (MbufI).
INTFLG (r) : Interrupt flag.
TXBI = 1 Indicates the TXBBUF needs a new data byte, cleared by writing TXBBUF.
RCBI = 1 Indicates the RCBBUF has received a new data byte, cleared by reading
RCBBUF.
SlvBMI = 1 Indicates the slave IIC address B matches condition.
TXAI = 1 Indicates the TXABUF needs a new data byte, cleared by writing TXABUF.
RCAI = 1 Indicates the RCABUF has received a new data byte, cleared by reading
RCABUF.
SlvAMI = 1 Indicates the slave IIC address A matches condition.
DbufI = 1 Indicates the DDC1 data buffer needs a new data byte, cleared by writing DBUF.
MbufI = 1 Indicates a byte is sent/received to/from the master IIC bus.
INTEN (w) : Interrupt enable.
ETXBI = 1 Enables TXBBUF interrupt.
ERCBI = 1 Enables RCBBUF interrupt.
ESlvBMI = 1 Enables slave address B match interrupt.
ETXAI = 1 Enables TXABUF interrupt.
ERCAI = 1 Enables RCABUF interrupt.
ESlvAMI = 1 Enables slave address A match interrupt.
Revision 0.9
- 17 -
2000/11/17
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